TMPR4937 datasheet(167/552 Pages) TOSHIBA

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Chapter 8 DMA Controller

8-11

8.3.7.2

Burst Transfer During Single Address Transfer

According to the SDRAM Controller and External Bus Controller specifications, the DMA

Controller cannot perform Burst transfer that spans across 32-double word boundaries.

Consequently, if the address that starts DMA transfer is not a multiple of the transfer setting size

(DMCCRn.XFSZ) (is not aligned), transfer cannot be performed by any of the transfer sizes that

were specified by a Burst transfer. Therefore, the DMA Controller executes multiple Burst

transactions of a transfer size smaller than the specified transfer size. This division method

changes according to the seting of the Transfer Size Mode bit (DMCCRn.USEXFSZ) of the DMA

Channel Control Register.

Figure 8.3.2 shows the Single Address Burst transfer status when the lower 8 bits of the

Transfer Start address are 0xA8 and the transfer setting size (DMCCRn.XFSZ) is set to 4 double

words.

Panel (a) of this figure shows the situation when the Transfer Size Mode bit

(DMCCRn.USEXFSZ) is “0”. In this case, first a three-double word transfer is performed up to

the address aligned to the transfer setting size. Then, four-double word transfer specified by the

transfer setting size is repeated. This setting is normally used.

On the other hand, panel (b) shows when the Transfer Size Mode bit (DMCCRn.USEXFSWZ)

is “1”. In this case, transfer is repeated according to the transfer setting size. Three-double word

transfer and one-double word transfer is only performed consecutively without releasing bus

ownership when transfer spans across a 32-double word boundary.

(a) DMCCRn.USEXFSZ

= “0”

(b) DMCCRn.USEXFSZ

= “1”

Figure 8.3.2 Non-aligned Single Address Burst Transfer

3 Double Words

4 Double Words

DMCCRn.XFER

= 4

32 Double Word Boundary

4 Double Words

+ 1) Double Words

4 Double Words

DMCCRn.XFER

= 4

4 Double Words

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