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TMPR4937 Datasheet(PDF) 172 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 172 Page - Toshiba Semiconductor |
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172 / 552 page ![]() Chapter 8 DMA Controller 8-16 (a) Address offset is equivalent (b) Address offset differs Figure 8.3.4 Dual Address Burst Transfer (DMCCRn.USEXFSZ = 0) a0 a8 b0 b8 c8 d0 d8 c0 e8 f0 f8 e0 00 08 10 18 28 30 38 20 63 0 20 28 30 38 48 50 58 40 68 70 78 60 80 88 90 98 a8 b0 b8 a0 63 0 Source Address FIFO (8 Double Words) Destination Address a0 a8 b0 b8 c8 d0 d8 c0 e8 f0 f8 e0 00 08 10 18 28 30 38 20 63 0 20 28 30 38 48 50 58 40 68 70 78 60 80 88 90 98 a8 b0 b8 a0 63 0 48 50 58 40 60 d0 d8 e0 c8 c0 |
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