TMPR4937 datasheet(181/552 Pages) TOSHIBA

181 / 552 page

Chapter 8 DMA Controller

8-25

8.4.1

DMA Master Control Register (DM0MCR, DM1MCR)

Offset address: DMAC0 0xB150, DMAC1 0xB950

This register controls the entire DMA Controller.

Reserved

: Type

: Initial value

Reserved

: Type

: Initial value

EIS[3:0]

DIS[3:0]

Reserved

FIFVC

: Type

0000

0000000

: Initial value

FIFVC

FIFWP

FIFRP

RSFIF

FIFUM[3:0]

Reserved

RRPT MSTEN

R/W

: Type

000

0000

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

63:32

Reserved

⎯

31:28

EIS[3:0]

Error Interrupt

Status

Error Interrupt Status [3:0] (Default: 0x0)

These four bits indicate the error interrupt status of each channel. EIS[n]

corresponds to channel n.

1: There is an error interrupt in the corresponding channel.

0: There is no error interrupt in the corresponding channel.

27:24

DIS[3:0]

Normal

Completion

Interrupt Status

Done Interrupt Status [3:0] (Default: 0x0)

These four bits indicate the transfer completion (transfer complete or chain

ended) interrupt status of each channel. DIS[n] corresponds to channel n.

1: There is a transfer completion interrupt in the corresponding channel.

0: There is no transfer completion interrupt in the corresponding channel.

23:21

Reserved

⎯

20:14

FIFVC

FIFO Valid Entry

Count

FIFO Valid Entry Count (Default: 0000000)

These read only bits indicate the byte count of data that were written to

FIFO but not read out from the FIFO.

13:11

FIFWP

FIFO Write

Pointer

FIFO Write Pointer (Default: 000)

These read only bits indicate the next write position in FIFO. This is a

diagnostic function.

10:8

FIFRP

FIFO Read

Pointer

FIFO Read Pointer (Default: 000)

These read only bits indicate the next read position in FIFO. This is a

diagnostic function.

RSFIF

Reset FIFO

Reset FIFO (Default: 0)

This bit is used for resetting FIFO. When this bit is set to “1”, the FIFO read

pointer, FIFO write pointer and FIFO valid entry count are initialized to “0”.

If an error occurs during DMA transfer, use this bit when data remains in

the FIFO (when the FIFO Valid entry Count Field is not “0”) to initialize the

FIFO.

R/W

Figure 8.4.1 DMA Master Control Register (1/2)

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