TMPR4937 datasheet(184/552 Pages) TOSHIBA

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Chapter 8 DMA Controller

8-28

Bit

Mnemonic

Field Name

Description

Read/Write

DBINH

Destination Burst

Inhibit

Destination Burst Inhibit (Default: 0)

During Dual Address transfer, this bit sets whether to perform Burst

transfer or Single transfer on a Write cycle to the address set from FIFO to

DMDARn when Burst transfer is set by DMCCRn.XFSZ. Refer to “8.3.8.2

Burst Transfer During Dual Address Transfer” for more information.

The settings of this bit have no effect during Single Address transfers.

1: Multiple Single transfers are executed.

0: Burst transfer is executed.

R/W

SBINH

Source Burst

Inhibit

Source Burst Inhibit (Default: 0)

During Dual Address transfer, this bit sets whether to perform Burst

transfer or Single transfer on a Read cycle to the FIFO from the address

set to DMSARn when Burst transfer is set by DMCCRn.XFSZ. Refer to

“8.3.8.2 Burst Transfer During Dual Address Transfer” for more

information.

The settings of this bit have no effect during Single Address transfers.

1: Multiple Single transfers are executed.

0: Burst transfer is executed.

R/W

CHRST

Channel Reset

Channel Reset (Default: 1)

This bit is used fo initializing channels. The DMCCRn.XFACT,

DMCCRn.CHNEN, and DMCSRn bits are all cleared. In addition, all

channel logic and interrupts from channels are cleared and bus ownership

requests to the DMA Channel Arbiter are also reset. The software must

clear this bit before operating a channel.

1: Reset channel

0: Enable channel

R/W

REVBYTE

Reverse Byte

Reverse Bytes (Default: 0)

This bit specifies whether to reverse the byte order during a Dual Address

transfer when the Transfer Setting Size field (DMCCRn.XFSZ) setting is 8

bytes or more. Refer to “8.3.8.3 Double Word Byte Swapping” for more

information.

1: Reverses the byte order.

0: Does not reverse the byte order.

R/W

ACKPOL

Acknowledge

Polarity

Acknowledge Polarity (Default: 0)

Specifies the polarity of the DMAACK[n] signal.

1: Asserts when the DMAACK[n] signal is High

0: Asserts when the DMAACK[n] signal is Low

R/W

REQPL

Request Polarity

Request Polarity (Default: 0)

Specifies the polarity of the DMAREQ[n] signal.

1: Asserts when the DMAREQ[n] signal is High.

0: Asserts when the DMAREQ[n] signal is Low.

R/W

EGREQ

Edge Request

Edge Request (Default: 0)

Specifies the method for detecting DMA requests by the DMAREQ[n]

signal.

1: DMAREQ[n] signal is Edge Detect.

0: DMAREQ[n] signal is Level Detect.

R/W

CHDN

Chain Complete

Chain Done (Default: 0)

Selects control by the DMADONE* signal. See “8.3.3.4 DMA Controller”

for more information.

1: Assertion of the DMADONE* signal controls the overall Chain DMA

transfer.

0: Assertion of the DMADONE* signal controls DMA transfer according to

the DMA Channel Register setting at that time.

R/W

18:17

DNCTL

DONE Control

Done Control (Default: 00)

Specifies the input/output mode of the DMADONE* signal. Refer to

“8.3.3.4 DMADONE* Signal” for more information.

00: DMADONE* signal becomes the input signal, but input is ignored.

01: DMADONE* signal becomes the input signal.

10: DMADONE* signal becomes the output signal.

11: DMADONE* signal becomes the open drain input/output signal.

R/W

Figure 8.4.2 DMA Channel Control Register (2/4)

TMPR4937 Datasheet(PDF) 184 Page - Toshiba Semiconductor

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