TMPR4937 datasheet(190/552 Pages) TOSHIBA

190 / 552 page

Chapter 8 DMA Controller

8-34

8.4.5

DMA Destination Address Register (DM0DARn, DM1DARn)

Offset Address: DMAC0 0xB010 (ch. 0) / 0xB050 (ch. 1) / 0xB090 (ch. 2) / 0xB0D0 (ch. 3)

DMAC1 0xB810 (ch. 0) / 0xB850 (ch. 1) / 0xB890 (ch. 2) / 0xB8D0 (ch. 3)

Reserved

: Type

: Initial value

Reserved

DADDR[35:32]

R/W

: Type

⎯

: Initial value

DADDR[31:16]

R/W

: Type

⎯

: Initial value

DADDR[15:0]

R/W

: Type

⎯

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

63:36

Reserved

⎯

35:0

DADDR

Destination

Address

Destination Address (Default: undefined)

This register sets the physical address of the transfer destination during

Dual Address transfer. This register is ignored during Single Address

transfer.

Refer to “8.3.8.1 Channel Register Settings During Dual Address Transfer”

for more information.

During Burst transfer, the value changes only by the size of data

transferred during each single bus operation. During Single transfer, the

value only changes by the value specified by the DMA Destination Address

Increment Register (DMDAIRn).

R/W

Figure 8.4.5 DMA Destination Address Register

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