TMPR4937 datasheet(193/552 Pages) TOSHIBA

Part #	TMPR4937

Description	64-Bit TX System RISC TX49 Family

PDF	552 Pages

Scroll/Zoom	100%

Manufacturer	TOSHIBA [Toshiba Semiconductor]

Direct Link	http://www.semicon.toshiba.co.jp/eng

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193 / 552 page

Chapter 8 DMA Controller

8-37

8.4.8

DMA Destination Address Increment Register (DM0DAIRn, DM1DAIRn)

Offset Address: DMAC0 0xB028 (ch. 0) / 0xB068 (ch. 1) / 0xB0A8 (ch. 2) / 0xB0E8 (ch. 3)

DMAC1 0xB828 (ch. 0) / 0xB868 (ch. 1) / 0xB8A8 (ch. 2) / 0xB8E8 (ch. 3)

Reserved

: Type

: Initial value

Reserved

: Type

: Initial value

Reserved

DADINC[23:16]

R/W

: Type

⎯

: Initial value

DADINC[15:0]

R/W

: Type

⎯

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

63:24

Reserved

⎯

23:0

DADINC

Destination

Address

Increment

Destination Address Increment (Default: undefined)

This field sets the increase/decrease value of the DMA Destination

Address Register (DMDARn). This value is a 24-bit two’s complement and

indicates a byte count.

Refer to “8.3.8.1 Channel Register Settings During Dual Address Transfer”

for more information.

R/W

Figure 8.4.8 DMA Destination Address Increment Register

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