ADS6223 datasheet(9/75 Pages) TI

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TIMING SPECIFICATIONS

(1)

ADS6225

,, ADS6224

ADS6223, ADS6222

SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007

Typical values are at 25

°C, min and max values are across the full temperature range T

MIN = –40°C to TMAX = 85°C, AVDD =

LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF

(2), I

O = 3.5 mA,

RL = 100 Ω

(3), no internal termination, unless otherwise noted.

ADS6225

ADS6224

ADS6223

ADS6222

TEST

PARAMETER

UNIT

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

Aperture jitter Uncertainty in the

250

fs rms

sampling instant

Interface: 2-wire, DDR bit clock, 14x serialization

From data

Data setup

tsu

cross-over to bit

0.35

0.55

0.45

0.65

0.85

0.8

1.1

time(4) (5)(6)

clock cross-over

From bit clock

Data hold

cross-over to data

0.35

0.58

0.5

0.7

0.9

0.8

1.1

time(4) (5)(6)

cross-over

Input clock rising

Clock

edge cross-over to

tpd_clk

propagation

3.4

4.4

5.4

3.4

4.4

5.4

3.4

4.4

5.4

3.4

4.4

5.4

frame clock rising

delay (6)

edge cross-over

Bit clock

cycle-cycle

350

ps pp

jitter (5)

Frame clock

cycle-cycle

ps pp

jitter (5)

Below specifications apply for 5 MSPS

≤ Sampling freq ≤ 125 MSPS and all interface options

Delay from input

Aperture

clock rising edge to

delay

the actual sampling

instant

Aperture

Channel-channel

delay

within same device

–250

±80

250

–250

±80

250

–250

±80

250

–250

±80

250

variation

Time for a sample

ADC Latency

to propagate to

Clock

(7)

ADC outputs, see

cycles

Figure 1

Time to valid data

after coming out of

100

μs

global power down

Time to valid data

Wake up time after input clock is

100

μs

re-started

Time to valid data

clock

after coming out of

200

cycles

channel standby

Data rise

From –100 mV to

tRISE

100

200

100

200

100

200

100

200

time

+100 mV

From +100 mV to

tFALL

Data fall time

100

200

100

200

100

200

100

200

–100 mV

Bit clock and

From –100 mV to

tRISE

Frame clock

100

200

100

200

100

200

100

200

+100 mV

rise time

(1)

Timing parameters are ensured by design and characterization and not tested in production.

(2)

CL is the External single-ended load capacitance between each output pin and ground.

(3)

Io Refers to the LVDS buffer current setting; RL is the external differential load resistance between the LVDS output pair.

(4)

Timing parameters are measured at the end of a 2 inch pcb trace (100-

Ω characteristic impedance) terminated by RLand CL.

(5)

Setup and hold time specifications take into account the effect of jitter on the output data and clock.

(6)

Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options.

(7)

Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as

listed in Table 28.

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