ADS6223 datasheet(13/75 Pages) TI

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(3/8) AVDD

ToParallelPin

AVDD

GND

(5/8) AVDD

DESCRIPTION OF PARALLEL PINS

ADS6225

,, ADS6224

ADS6223, ADS6222

SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007

Table 4. Priority Between Parallel Pins and Serial Registers

FUNCTIONS SUPPORTED

PRIORITY

CFG1 to

As described in Table 9 to

CFG4

Table 12

LOW, then the control voltage on these parallel pins determines the function as per Tables

D0 Bit of register 0x00 controls Power down global ONLY if PDN pin is LOW. If PDN is high,

PDN

Global power down

device is in global power down mode.

Coarse Gain setting is controlled by bit D5 of register 0x0D ONLY if the <OVRD> bit is high.

Else, it is in default register setting of 0 dB COARSE GAIN.

SEN

Serial Interface Enable

Internal/external reference setting is determined by bit D6 of register 0x00.

D7, D6, D5 Bits of register 0x0A control the sync and deskew output patterns.

SCLK,

Serial Interface Clock and

SDATA

Serial Interface Data pins

Power down is determined by bit D0 of 0x00 register.

Figure 3. Simple Scheme to Configure Parallel Pins

Table 5. SCLK, SDATA Control Pins

SCLK

SDATA

DESCRIPTION

LOW

NORMAL conversion.

SYNC – ADC Outputs sync pattern on all channels. This pattern can be used by the receiver to align the

LOW

HIGH

deserialized data to the frame boundary. See Capture Test Patterns for details.

POWER DOWN – Global power down, all channels of the ADC are powered down, including internal references,

HIGH

LOW

PLL and output buffers.

DESKEW – ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure

HIGH

deserializer uses the right clock edge. See Capture Test Patterns for details.

Table 6. SEN Control Pin

SEN

DESCRIPTION

External reference and 0 dB coarse gain (full-scale = 2 Vpp)

(3/8)LVDD

External reference and 3.5 dB coarse gain (full-scale = 1.34 Vpp)

(5/8)LVDD

Internal reference and 3.5 dB coarse gain (full-scale = 1.34 Vpp)

LVDD

Internal reference and 0 dB coarse gain (full-scale = 2 Vpp)

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