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ADS6223 Datasheet(PDF) 18 Page - Texas Instruments |
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ADS6223 Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 75 page  www.ti.com DESCRIPTION OF SERIAL REGISTERS ADS6225 ,, ADS6224 ADS6223, ADS6222 SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007 Table 14. REGISTER BITS ADDRESS A4–A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 <REF> <PDN> <PDN CHB> <PDN CHA> <RST> INTERNAL GLOBAL 00 0 0 0 0 0 POWER POWER 0 S/W RESET OR POWER DOWN CHB DOWN CH A EXTERNAL DOWN D0 - D4 Power down modes D0 <PDN GLOBAL> 0 Normal operation 1 Global power down, including all channels ADCs, internal references, internal PLL and output buffers D2 <PDN CHA> 0 CH A Powered up 1 CH A ADC Powered down D3 <PDN CHB> 0 CH B Powered up 1 CH B ADC Powered down D5 <REF> Reference 0 Internal reference enabled 1 External reference enabled D10 <RST> 1 Software reset applied – resets all internal registers and self-clears to 0 18 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222 |
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