ADS6223 datasheet(16/75 Pages) TI

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SERIAL INTERFACE TIMING CHARACTERISTICS

RESET TIMING

T0108-03

PowerSupply

AVDD,LVDD

RESET

SEN

ADS6225

,, ADS6224

ADS6223, ADS6222

SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007

Typical values at 25

°C, min and max values across the full temperature range T

MIN = –40°C to TMAX = 85°C, AVDD = LVDD =

3.3 V, unless otherwise noted.

PARAMETER

MIN

TYP

MAX

UNIT

fSCLK

SCLK Frequency, fSCLK = 1/tSCLK

> DC

MHz

tSLOADS

SEN to SCLK Setup time

tSLOADH

SCLK to SEN Hold time

tDSU

SDATA Setup time

tDH

SDATA Hold time

Time taken for register write to take effect after 16th SCLK falling edge

100

Typical values at 25

°C, min and max values across the full temperature range T

MIN = –40°C to TMAX = 85°C, AVDD = LVDD =

3.3 V, unless otherwise noted.

PARMATER

CONDITIONS

MIN

TYP

MAX

UNIT

Power-on delay time

Delay from power-up of AVDD and LVDD to RESET pulse active

Reset pulse width

Pulse width of active RESET signal

Delay from RESET disable to SEN active

tPO

Power-up delay time

Delay from power-up of AVDD and LVDD to output stable

6.5

Figure 5. Reset Timing

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Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

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