ADS6223 datasheet(21/75 Pages) TI

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ADS6225

,, ADS6224

ADS6223, ADS6222

SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007

Bit clock capture edge (only when SDR bit clock is selected, D1 = 1)

Capture data with falling edge of bit clock

Capture data with rising edge of bit clock

<COARSE GAIN>Coarse gain control

0 dB Coarse gain

3.5dB Coarse gain (Full-scale range = 1.34 Vpp)

MSB or LSB first selection

MSB First

LSB First

Byte/bit wise outputs (only when 2-wire is selected)

Byte wise

Bit wise

D10

<OVRD> Over-ride bit. All the functions in register 0x0D can also be controlled using the

parallel control pins. By setting bit <OVRD> = 1, the contents of register 0x0D will over-ride

the settings of the parallel pins.

Disable over-ride

Enable over-ride

Table 20.

BITS

ADDRESS

A4–A0

D10

LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS

LVDS CURRENT SETTINGS

LVDS CURRENT DOUBLE

<CURR DOUBLE> LVDS current double for data outputs

Nominal LVDS current, as set by <D5…D2>

Double the nominal value

<CURR DOUBLE> LVDS current double for bit and word clock outputs

Nominal LVDS current, as set by <D5…D2>

Double the nominal value

D3–D2

<LVDS CURR> LVDS current setting for data outputs

3.5 mA

4 mA

2.5 mA

3 mA

D5–D4

<LVDS CURR> LVDS current setting for bit and word clock outputs

3.5 mA

4 mA

2.5 mA

3 mA

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