ADS6223 datasheet(17/75 Pages) TI

17 / 75 page

www.ti.com

SERIAL REGISTER MAP

ADS6225

,, ADS6224

ADS6223, ADS6222

SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007

Table 13. Summary of Functions Supported By Serial Interface

(1) (2)

ADDRESS

A4–A0

D10

<PDN

<REF>

GLOBAL>

<RST>

INTERNAL

POWER

GLOBAL

S/W RESET

DOWN CHB

DOWN CH A

POWER

EXTERNAL

DOWN

INPUT CLOCK BUFFER GAIN CONTROL

<DF>

DATA

FORMAT 2S

COMP OR

TEST PATTERNS

STRAIGHT

BINARY

CUSTOM PATTERN (LOWER 11 BITS)

<CUSTOM

CUSTOM

FINE GAIN CONTROL (1dB to 6 dB)

PATTERN

(MSB BIT)

<COARSE

FALLING OR

<OVRD>

BYTE-WISE

GAIN>

RISING BIT

12-BIT OR

DDR OR

1-WIRE OR

MSB OR

OVERRIDE

COURSE

CLOCK

14-BIT

SDR BIT

2-WIRE

LSB FIRST

BIT

BIT-WISE

GAIN

CAPTURE

SERIALIZE

CLOCK

INTERFACE

ENABLE

EDGE

LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS

LVDS CURRENT SETTINGS

LVDS CURRENT DOUBLE

WORD-WISE CONTROL

LVDS INTERNAL TERMINATION - DATA OUTPUTS

(1)

The unused bits in each register (shown by blank cells in above table) must be programmed as 0.

(2)

Multiple functions in a register can be programmed in a single write operation.

Submit Documentation Feedback

Product Folder Link(s): ADS6225 ADS6224 ADS6223 ADS6222

ADS6223 Datasheet(PDF) 17 Page - Texas Instruments

ADS6223 Datasheet(HTML) 17 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

Datasheet Download

Link URL