ADS6223 datasheet(24/75 Pages) TI

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ADS6225

,, ADS6224

ADS6223, ADS6222

SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007

PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued)

PINS

NO. OF

I/O

DESCRIPTION

PINS

NAME

NO.

This pin functions as serial interface clock input when RESET is low.

When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes

SCLK

(along with SDATA). See Table 5 for description.

This pin has an internal pull-down resistor.

This pin functions as serial interface data input when RESET is low.

When RESET is high, it controls DESKEW, SYNC and global POWER DOWN modes

SDATA

(along with SCLK). See Table 5 for description.

This pin has an internal pull-down resistor.

This pin functions as serial interface enable input when RESET is low.

When RESET is high, it controls coarse gain and internal/external reference modes. See

SEN

Table 6 for description.

This pin has an internal pull-up resistor.

Serial interface reset input.

When using the serial interface mode, the user MUST initialize internal registers through

hardware RESET by applying a high-going pulse on this pin or by using software reset

RESET

option. Refer to the Serial Interface section. In parallel interface mode, tie RESET

permanently high. (SCLK, SDATA and SEN function as parallel control pins in this mode).

The pin has an internal pull-down resistor to ground.

PDNA

Channel A ADC power down control pin.

PDNB

Channel B ADC power down control pin.

Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock

CFG1

selection. See Table 9 for description.

Tie to AVDD for 2-wire interface with DDR bit clock.

Parallel input pin. It controls 12x or 14x serialization and SDR bit clock capture edge. See

CFG2

Table 10 for description.

For 12x serialization with DDR bit clock, tie to ground or AVDD.

CFG3

RESERVED pin - TIE to ground.

Parallel input pin. It controls data format and MSB or LSB first modes. See Table 12 for

CFG4

description.

Internal reference mode – common-mode voltage output

VCM

External reference mode – reference input. The voltage forced on this pin sets the internal

reference.

OUTPUT PINS

DA0_P,DA0_M

47,48

Channel A differential LVDS data output pair, wire 0

DA1_P,DA1_M

45,46

Channel A differential LVDS data output pair, wire 1

DB0_P,DB0_M

39,40

Channel B differential LVDS data output pair, wire 0

DB1_P,DB1_M

37,38

Channel B differential LVDS data output pair, wire 1

DCLKP,DCLKM

43,44

Differential bit clock output pair

FCLKP,FCLKM

41,42

Differential frame clock output pair

Do Not Connect

Connect to ground plane using multiple vias. Refer to Board Design Considerations in

PAD

application section

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