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AM625 Datasheet(PDF) 192 Page - Texas Instruments

Part # AM625
Description  AM62x Sitara™ Processors
PDF  276 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

AM625 Datasheet(HTML) 192 Page - Texas Instruments

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6.12.5.16.2 MMC1/MMC2 - SD/SDIO Interface
MMC1/MMC2 interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical
Layer Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:
• Default speed
• High speed
• UHS–I SDR12
• UHS–I SDR25
• UHS–I SDR50
• UHS–I DDR50
• UHS–I SDR104
Table 6-100 presents the required DLL software configuration settings for MMC1/2 timing modes.
Table 6-100. MMC1/MMC2 DLL Delay Mapping for all Timing Modes
REGISTER NAME
MMCSD1_MMC_SSCFG_PHY_CTRL_4_REG
MMCSD2_MMC_SSCFG_PHY_CTRL_4_REG
BIT FIELD
[20]
[15:12]
[8]
[4:0]
BIT FIELD NAME
OTAPDLYENA
OTAPDLYSEL
ITAPDLYENA
ITAPDLYSEL
MODE
DESCRIPTION
DELAY
ENABLE
DELAY
VALUE
INPUT
DELAY
ENABLE
INPUT
DELAY
VALUE
Default
Speed
4-bit PHY
operating
3.3V, 25MHz
NA(1)
NA(1)
0x1
0x0
High
Speed
4-bit PHY
operating
3.3V, 50MHz
NA(1)
NA(1)
0x1
0x0
UHS-I
SDR12
4-bit PHY
operating
1.8V, 25MHz
0x1
0xF
0x1
0x0
UHS-I
SDR25
4-bit PHY
operating
1.8V, 50MHz
0x1
0xF
0x1
0x0
UHS-I
SDR50
4-bit PHY
operating
1.8V, 100MHz
0x1
0xC
0x1
Tuning(2)
UHS-I
DDR50
4-bit PHY
operating
1.8V, 50MHz
0x1
0x9
0x1
Tuning(2)
UHS-I
SDR104
4-bit PHY
operating
1.8V, 200MHz
0x1
0x6
0x1
Tuning(2)
(1)
NA means this register field has no function when operating with half-cycle timing, which is required for this mode.
(2)
Tuning means this mode requires a tuning algorithm to be used to determine optimal input timing
AM625, AM625-Q1, AM623, AM620-Q1
SPRSP58C – JUNE 2022 – REVISED OCTOBER 2025
www.ti.com
192
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Copyright © 2025 Texas Instruments Incorporated
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1



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