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AM625 Datasheet(PDF) 122 Page - Texas Instruments

Part # AM625
Description  AM62x Sitara™ Processors
PDF  276 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

AM625 Datasheet(HTML) 122 Page - Texas Instruments

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To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract
the combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO
to determine the value of CL2. For example, if CL = 10pF, CPCBXI = 2.9pF, CXI = 0.5pF, CPCBXO = 3.7pF, CXO =
0.5pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10pF) - 2.9pF - 0.5pF)] = 16.6pF and CL2 = [(2CL) -
(CPCBXO + CXO)] = [(2 × 10pF) - 3.7pF - 0.5pF)] = 15.8pF
6.12.4.1.1.2 Shunt Capacitance
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for
MCU_OSC0 operating conditions defined in Table 6-22. Shunt capacitance, Cshunt, of the crystal circuit is a
combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal
circuit components to MCU_OSC0 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB
designer should be able to extract mutual parasitic capacitance between these signal traces. The device
package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined
in Table 6-23.
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can
also be minimized by placing a ground trace between these signals when the layout requires them to be routed
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as
possible when selecting a crystal.
AM65x_MCU_OSC_SC_06
Device
MCU_OSC0_XO
MCU_OSC0_XI
C
PCBXIXO
PCB
Signal Traces
Crystal Circuit
Components
C
XIXO
C
O
Figure 6-19. Shunt Capacitance
A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt
capacitance specified by the crystal manufacturer.
Cshunt ≥ CO + CPCBXIXO + CXIXO
For example, the equation would be satisfied when the crystal being used is 25MHz with an ESR = 30Ω,
CPCBXIXO = 0.04pF, CXIXO = 0.01pF, and shunt capacitance of the crystal is less than or equal to 6.95pF.
AM625, AM625-Q1, AM623, AM620-Q1
SPRSP58C – JUNE 2022 – REVISED OCTOBER 2025
www.ti.com
122
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Copyright © 2025 Texas Instruments Incorporated
Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1



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