AM625 datasheet(128/276 Pages) TI2

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6.12.4.2 Output Clocks

The device provides several system clock outputs. Summary of these output clocks are as follows:

• MCU_SYSCLKOUT0

– MCU_PLL0_HSDIV0_CLKOUT (MCU_SYSCLKOUT0) divided by 4 and sent out of the device as

MCU_SYSCLKOUT0. This clock output is provided for test and debug purposes only.

• MCU_OBSCLK0

– Observation clock output for test and debug purposes only.

• WKUP_CLKOUT0

– WKUP domain CLKOUT0 output.

• SYSCLKOUT0

– MAIN_PLL0_HSDIV0_CLKOUT (SYSCLKOUT0) divided by 4 and then sent out of the device as

SYSCLKOUT0. This clock output is provided for test and debug purposes only.

• CLKOUT0

– CLKOUT0 is the Ethernet subsystem clock (MAIN_PLL2_HSDIV1_CLKOUT) divided-by-5 or divided-

by-10. This clock output was provided as an optional source to the external PHY. When configured

to operate as the RMII Clock source (50MHz) the signal must also be routed back to the respective

RMII[x]_REF_CLK pin for proper device operation.

• OBSCLK0

– Observation clock output for test and debug purposes only.

• AUDIO_EXT_REFCLK[1:0]

– Option of sourcing one of six McASP high-frequency audio reference clocks,

MAIN_PLL1_HSDIV6_CLKOUT, or MAIN_PLL2_HSDIV8_CLKOUT when configured to operate as an

output.

6.12.4.3 PLLs

Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from

off-chip power-sources.

There is one PLL in the MCU domain:

• MCU_PLL0 (MCU PLL)

There are eight PLLs in the MAIN domain:

• MAIN_PLL0 (MAIN PLL)

• MAIN_PLL1 (PER0 PLL)

• MAIN_PLL2 (PER1 PLL)

• MAIN_PLL8 (ARM0 PLL)

• MAIN_PLL12 (DDR PLL)

• MAIN_PLL15 (SMS_PLL)

• MAIN_PLL16 (DSS0 PLL)

• MAIN_PLL17 (DSS1 PLL)

The system designer should consider the reference clock source start-up time and the PLL lock requirements

before configuring and using any of the PLL outputs as clock sources. The device reference clock input

requirements are defined in Section 6.12.4.1, Input Clocks / Oscillators. PLL configuration details are described

in the device TRM.

For more information on PLLs, see the PLL subsection in the Clocking subsection of the Device Configuration

section in the device TRM.

AM625, AM625-Q1, AM623, AM620-Q1

SPRSP58C – JUNE 2022 – REVISED OCTOBER 2025

www.ti.com

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