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AM625 Datasheet(PDF) 138 Page - Texas Instruments |
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AM625 Datasheet(HTML) 138 Page - Texas Instruments |
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138 / 276 page ![]() 6.12.5.4 DDRSS For more details about features and additional description information on the device (LP)DDR4 Memory Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Table 6-43 and Figure 6-34 present switching characteristics for DDRSS. Table 6-43. DDRSS Switching Characteristics see Figure 6-34 NO. PARAMETER DDR TYPE MIN MAX UNIT 1 tc(DDR_CKP/ DDR_CKN) Cycle time, DDR_CKP and DDR_CKN LPDDR4 1.25(1) 20 ns DDR4 1.25(1) 1.6 ns (1) Minimum DDR clock Cycle time will be limited based on the specific memory type (vendor) used in a system and by PCB implementation. Refer to DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency. DDR0_CKP 1 DDR0_CKN Figure 6-34. DDRSS Switching Characteristics For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM. AM625, AM625-Q1, AM623, AM620-Q1 SPRSP58C – JUNE 2022 – REVISED OCTOBER 2025 www.ti.com 138 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: AM625 AM625-Q1 AM623 AM620-Q1 |
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