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PAC1721 Datasheet(PDF) 37 Page - Microchip Technology |
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PAC1721 Datasheet(HTML) 37 Page - Microchip Technology |
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37 / 92 page ![]() 2026 Microchip Technology Inc. and its subsidiaries DS-20007088A-page 37 PAC1721 6.1 Reading Data Bytes Data represented by the data registers becomes read- able 1 µs after a conversion cycle completes and a Refresh (any) command is issued. When new data is written to a configuration register and the host reads it back, the new data is read back even if no Refresh (any) command was issued to trigger the new data to take effect. Check the following registers to ensure that the active and latched configurations are known: • CONTROL_ACT • NEG_PWR_FSR_ACT • CONTROL_LAT • NEG_PWR_FSR_LAT 6.2 Register Categories The PAC1721 registers can be categorized as follows: • Data Registers: ◦ ACC_COUNT ◦ VACC ◦ VBUS ◦ VSENSE ◦ VBUS_AVG ◦ VSENSE_AVG ◦ VPOWER ◦ VBUS_MIN ◦ VBUS_MAX ◦ VSENSE_MIN ◦ VSENSE_MAX ◦ VPOWER_MIN ◦ VPOWER_MAX • Configuration Registers: ◦ CONTROL ◦ NEG_PWR_FSR ◦ SLOW ◦ SLOW_ALERT0 ◦ GPIO_ALERT1 ◦ ACC_FULL_LIMIT ◦ ALERT_ENABLE ◦ ACC_COUNT_PRESET ◦ VACC_PRESET |
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