PAC1721 datasheet(66/92 Pages) MICROCHIP

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PAC1721

DS-20007088A-page 66

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NEG_PWR_FSR_ACT (ADDRESS 18H)

U-0

R-0

–

CFG_VS[1:0]

CFG_VB[1:0]

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as 0

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

X = Bit is unknown

This register contains an image of the NEG_PWR_FSR. This register reflects the settings that are currently active.

The values in the NEG_PWR_FSR register can be programmed, but not yet activated by a Refresh (any) command,

while the values in the NEG_PWR_FSR_LAT register are the settings active before receiving a Refresh (any) command.

This register allows to determine the actual active settings.

This register becomes valid when the results registers are valid following a Refresh (any) command issued after a

conversion cycle completes.

bit 7:4

Unimplemented at this time. Always reads 0.

bit 3:2

CFG_VS[1:0]: Configure FSR for VSENSE measurements.

00b = VSENSE is in Unipolar 0-FSR mode: 0V to +100 mV FSR (default)

01b = VSENSE is in Bipolar ± FSR mode: –100 mV to +100 mV FSR

10b = VSENSE is in Bipolar ± FSR/2 mode: –50 mV to +50 mV FSR/2

11b = Reserved

bit 1:0

CFG_VB[1:0]: Configure FSR for VBUS measurements.

00b = VBUS is in Unipolar 0-FSR mode: 0V to +9V FSR (default)

01b = VBUS is in Bipolar ± FSR mode: –9V to +9V FSR

10b = VBUS is in Bipolar ± FSR/2 mode: –4.5V to +4.5V FSR/2

11b = Reserved

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