PAC1721 datasheet(13/92 Pages) MICROCHIP

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DS-20007088A-page 13

PAC1721

3.0

PIN DESCRIPTIONS

Table 3-1 describes the pins of PAC1721.

3.1

Sense Voltage Pins

(VSENSE+ and VSENSE–)

Pins VSENSE+ and VSENSE– form the differential

input for measuring voltage across RSHUNT in the

circuit application.

3.2

Ground Pin (GND)

This pin is the system ground.

3.3

Positive Power Supply Voltage Pin

(VDD)

This is the power supply input pin for PAC1721. It has

a voltage range of 2.7V to 5.5V. Bypass it with a 100 nF

ceramic capacitor connected to GND near the IC.

3.4

SMBus Data (SMBDAT) Pin (SDA)

This is the bidirectional SMBus data pin. This pin is

open-drain and requires a pull-up resistor connected to

the external communication voltage rail.

3.5

SMBus Clock (SMBCLK) Pin (SCL)

This is the SMBus clock input pin and requires an

external pull-up resistor, except if used in High-speed

mode, which requires a CMOS driver from the host.

3.6

A0 and A1 Multi-functional Pins

These pins are used to define the I2C/SMBus address.

When pulled high through a resistor to VDD, the A0 or

A1 pin can be used as an ALERT, SLOW or GPIO pin.

These pins are an open-drain configuration.

3.7

Power-down Pin (PWRDN)

When this pin is pulled low, PAC1721 enters the Power-

down state. In this state, all the circuitry powers down,

including the SMBus pins.

3.8

Positive Bus Voltage Pin (VBUS+)

This pin is the input pin for VBUS. It can be used as

either a high-side or a low-side power monitor.

TABLE 3-1:

PAC1721 PIN DESCRIPTIONS

Pin Number

Symbol

Description

8-Lead

VDFN

10-Lead

VDFN

VSENSE+

Analog input pin. 0 to FSR.

Connect to source side of the shunt resistor (RSHUNT).

VSENSE– Analog input pin. 0 to FSR. Connect to load side of RSHUNT.

GND

Ground pin for the integrated circuit (IC).

VDD

IC power pin.

SCL

SMBus clock input pin.

SDA

SMBus data I/O pin.

Multifunction pin. Digital I/O. Address 0, ALERT, SLOW and GPIO pin.

Multifunction pin. Digital I/O. Address 1, ALERT, SLOW and GPIO pin.

—

PWRDN

When this pin becomes active low, PAC1721 enters power-down state.

Hardware triggered POR.

—

VBUS+

Analog input pin. Connect to VBUS.

Configurable for high-side or low-side power monitoring.

Note:

8-Lead VDFN only: Pin VSENSE+ also

acts as the input pin for VBUS

Note 1: 10-Lead VDFN only

2: Maximum voltage on this pin is VDD.

Do not pull this pin up to voltages that

exceed VDD

Note:

This pin is available only for the 10-Lead

VDFN.

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