PAC1721 datasheet(58/92 Pages) MICROCHIP

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PAC1721

DS-20007088A-page 58

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bit 4

POR: This bit allows to determine if PAC1721 reset after it was programmed.

This bit can be cleared after a POR event and then used to determine if PAC1721 was powered cycled

or reset since the latest POR event.

If a reset is detected in this manner, any non-default programming can be reconfigured.

This bit is reset only by an internal POR event.

0b = This bit was cleared over I2C since the latest POR event occurred.

1b = A POR event occurred and this bit was not cleared since then. (default)

bit 3

TIMEOUT: Enable or disable the SMBus timeout functionality. For more details, see Section 5.2.

0b = Disables SMBus timeout. (default)

1b = Enables SMBus timeout.

bit 2

BYTE COUNT: This bit enables the response to the SMBus Block Read command for each register

read to include the byte count data. For more details, see Section 5.6.9.

0b = No byte count data included in the response to a Block Read command. (default)

1b = Byte count data included in the response to a Block Read command.

bit 1

Unimplemented at this time. Always reads 0.

bit 0

I2C_HISPEED: This bit enables 3.4 MHz I2C High-speed mode operation by changing the pulse width

parameters of the Spike Suppression (tSP) from a maximum of 50 ns to 10 ns.

High-speed mode allows the SMBus clock to run at 3.4 MHz.

Note:

Due to the changes to communication parameters when entering and exiting High-speed

mode, do not program this bit as part of a Block Write. If this bit is disabled, PAC1721

NACKs the sent command, but the command is still accepted.

0b = PAC1721 operates in 1 MHz I2C Fast-mode Plus mode. (default)

1b = PAC1721 operates in 3.4 MHz I2C High-speed mode.

PAC1721 Datasheet(PDF) 58 Page - Microchip Technology