TCC76 datasheet(110/259 Pages) ETC2

110 / 259 page

TCC76x

Specification Rev. 0.07

February 23, 2005

32-bit RISC Microprocessor for Digital Media Player

CLOCK GENERATOR

Preliminary

8-4

8.2 Register Description

Table 8.2 Clock Generator Register Map (Base Address = 0x80000400)

Name

Address

Type

Reset

Description

CKCTRL

0x00

R/W

0x00007FFE

Clock Control Register

PLLMODE

0x04

R/W

0x00002E02

PLL Control Register

SCLKmode

0x08

R/W

0x00082000

System Clock Control Register

DCLKmode

0x0C

R/W

0x00000800

DCLK (DAI/CODEC) Control Register

EACLKmode

0x10

R/W

0x00000000

ADCLK and EX2CLK Control Register

EX1CLKmode

0x14

R/W

0x00000000

EX1CLK Control Register

UTCLKmode

0x18

R/W

0x000001BE

UTCLK (UART) Control Register

UBCLKmode

0x1C

R/W

0x00000000

UBCLK (USB) Control Register

LCLKmode

0x20

R/W

0x00000000

LCLK (LCD) Control Register

TCLKmode

0x24

R/W

0x00000000

TCLK (Timer) Control Register

GCLKmode

0x28

R/W

0x00000000

GCLK (GSIO) Control Register

CIFCLKmode

0x2C

R/W

0x00000000

CIFCLK Control Register

SW_nRST

0x3C

R/W

0x0000FEFF

Software Reset for each peripherals

PWDCTL

0x40

R/W

0x00000000

Power Down Control

DIVMODE

0x44

R/W

0x00000000

Divider Mode Enable (DCO Disable)

HCLKSTOP

0x48

R/W

0x00000000

HCLK Stop Control

XIN

MUX

Divider

XTIN

PLL

DCO /

Divider

MUX

FCLK

DCO /

Divider

MUX

HCLK to CPU

•

MUX

DCO /

Divider

MUX

DCLK

PLLOUT

PLLDIVCLK

MUX

PLLmode[18]

PW DCTL[17]

(XTFCLK)

SCLKmode[15] ? PW DCTL[17] :

PW DCTL[16]

SCLKmode[5:0] (F_PHASE)

SCLKmode[13:8] (H_PHASE)

DCO/Divider selected if (SCLKmode[13:8] != 0)

PW DCTL[9:8] (DVPLL)

XTIN is selected if PW DCTL[7] (XTTC32) == 0

DIVCLK1

DIVCLK0

DCLKmode[13:0] (D_PHASE)

DCLKmode[15:14] (DIVD)

DCO/Divider selected if (SCLKmode[5:0] != 0)

!CKCTRL[24]

!CKCTRL[24] |

SCLKmode[14]

HCLKSTOP[14:0]

!CKCTRL[1]

!CKCTRL[11] (PLL)

!CKCTRL[12] &

(!CKCTRL[25] | PLLmode[19])

ZCLK

(32-bit Counter Clock)

Gated

HCLK to

each

peripheral

!CKCTRL[25]

!PW DCTL[7] |

!CKCTRL[12] &

(!CKCTRL[25] | PLLmode[19])

Figure 8.2 Clock Generator Register Signals

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