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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
CLOCK GENERATOR
Preliminary
8-1
8 CLOCK GENERATOR
8.1 Overview
The TCC76x has a lot of peripherals with different operating frequency. To provide an appropriate clock to
each peripheral, the TCC76x has a clock generator unit. There is also a power management feature that can
manage several operating modes, such as initialization mode, normal operation mode, idle mode, stop mode.
WAITGEN
XIN
WAIT
PLL
PLLOUT
FCLK (CPU)
HCLK (AHB)
DCLK GEN
DCLK (GSIO)
UTCLK
GEN
USBCLK
GEN
UTCLK (UART)
UHCLK (USB Host)
UDCLK (USB Device)
DCLKmode
UTCLKmode
UBCLKmode
SCLKmode[13:8]
PWRDN
PLLmode
LCLK GEN
LCLK (LCD)
PXCLKmode
i_XIN
DIVCLK1
XTIN
EX2CLK (I2C)
EX2CLK
GEN
EX2CLKmode
TCLK GEN
TCLKmode
TCLK (Timer/Counter)
[18]
GCLK GEN
GCLKmode
GCLK (DAI)
MUX
MUX
MUX
MUX
MUX
MUX
MUX
[15:14]
[15:14]
[15:14]
[9:8]
[9:8]
[9:8]
[9:8]
EX1CLK (External)
EX1CLK
GEN
EX1CLKmode
MUX
[15:14]
ADCLK
GEN
ADCLKmode
ADCLK (ADC)
MUX
[7:6]
HCLK GEN
FCLK GEN
CIFCLK
GEN
CIFCLKmode
CIFCLK (Camera I/F)
MUX
[7:6]
SCLKmode[5:0]
Divider
DIVCLK0
PLLDIVCLK
MUX
MUX
MUX
MUX
PWDCTL[17]
PWDCTL[16]
PWDCTL[9:8]
Figure 8.1 Clock Generator Block Diagram
WAITGEN module is for waiting until oscillation is stabilized. It blocks internal clocks until about 218
transitions occur on XIN after reset is released. If frequency of XIN is 16MHz, the wait time is about 16.4 ms
(21.85ms @12MHz). The source of the system clocks (FCLK and HCLK) can be selected among XIN (main
oscillator), PLLOUT (PLL output clock) and XTIN (sub-oscillator). The other clocks that are dedicated to each
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