TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
CLOCK GENERATOR
Preliminary
8-15
Divider Mode Enable Register (DIVMODE)
0x80000444
Bit
Name
Type Default Description
31:13 Reserved
R
0
12
DVMCIF
R/W
0
Divider Mode Enable for CIF Clock (CIFCLK)
11
DVMGSIO
R/W
0
Divider Mode Enable for GSIO Clock (GCLK)
10
DVMTC
R/W
0
Divider Mode Enable for Timer/Counter Clock (TCLK)
9
DVMLCD
R/W
0
Divider Mode Enable for LCD Clock (LCLK)
8
DVMUSB
R/W
0
Divider Mode Enable for USB Clock (UHCLK, UDCLK)
7
DVMUART
R/W
0
Divider Mode Enable for UART/IrDA Clock (UTCLK)
6
DVMEXT
R/W
0
Divider Mode Enable for External Clock (EX1CLK)
5
DVMADC
R/W
0
Divider Mode Enable for ADC Clock (ADCLK)
4
DVMI2C
R/W
0
Divider Mode Enable for I2C Clock (EX2CLK)
3
DVMDAI
R/W
0
Divider Mode Enable for DAI Clock (DCLK)
2
Reserved
R/W
0
1
DVMAHB
R/W
0
Divider Mode Enable for AHB Clock (HCLK)
0
DVMCPU
R/W
0
Divider Mode Enable for CPU Clock (FCLK)
Each bit selects clock division mode of corresponding clock generator. When set to high, DCO mode is disabled and
the clock generator works as a simple divider. The PHASE field of the following registers are used as divisor values;
SCLKmode
DCLKmode
EACLKmode
EX1CLKmode
UTCLKmode
UBCLKmode
LCLKmode
TCLKmode
GCLKmode
CIFCLKmode
The clock generator output frequency is determined by the following equation.
fOUT = fMUX / (PHASE + 1)
Where, fMUX is the frequency of multiplexer output (refer to Figure 8.1).
As described above, PHASE field has different meaning in the two modes. DIVMODE register should be
programmed only when the corresponding clock is disabled or PHASE value is “0” (fOUT = fMUX). Otherwise,
unexpected clock frequency is fed to core modules until correct PHASE value is written.
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