TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
CLOCK GENERATOR
Preliminary
8-13
CIFCLK Control Register (CIFCLKmode)
0x8000042C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
DIVCIF
0
CIF_PHASE[5:0]
Bit
Name
Type Default Description
31:10 Reserved
R
0
Reserved
9:8
DIVCIF
R/W
0
CIFCLK Divisor Clock Select
DIVCIF fDIVCIF (Divisor Clock Source Selected)
0
XIN input
1
PLL output
2
XTIN input
3
PLLDIVCLK (PLL clock divider output)
7:6
Reserved
R
0
Reserved
5:0
CIF_PHASE
R/W
0
CIFCLK Clock Frequency Select
DIVMODE[12]
CIF_PHASE
fCIFCLK (CIFCLK Frequency)
0
0
fDIVCIF
0
1 ~ 0x20
fDIVCIF * CIF_PHASE / 2
6
0
> 0x20
Undefined. Do not use.
1
X
fDIVCIF / (CIF_PHASE + 1)
CIFCLK is also controlled by CIF bit of CKCTRL register that can enable or disable CIFCLK. If this bit is set to high,
CIFCLK is disabled and if it is low, CIFCLK is enabled.
Software Reset Register (SW_nRST)
0x8000043C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CIF LCD DMA UBH ETC ECC FGP
I2C
GS
UT
UB
GP
TC
IC
DAI
This register can be used to generate a reset signal within a certain peripheral. If one of bits in this register is set
to 0, the corresponding peripheral is initialized as like as a system reset has been issued and remained in
initialization state until the corresponding bit is released back to 1.
Bit
Name
Type Default Description
14
CIF
R/W
1
CIF Block Reset Control
13
LCD
R/W
1
LCD Block Reset Control
12
DMA
R/W
1
DMA Block Reset Control
11
UBH
R/W
1
USB Host Block Reset Control
10
ETC
R/W
1
Miscellaneous Block Reset Control.
9
ECC
R/W
1
ECC Block Reset Control
8
FGP
R/W
0
Fast GPIO Block Reset Control
7
I2C
R/W
1
I2C Block Reset Control
6
GS
R/W
1
GSIO Block Reset Control
5
UT
R/W
1
UART/IrDA Block Reset Control
4
UB
R/W
1
USB Device Block Reset Control
3
GP
R/W
1
GPIO Block Reset Control
2
TC
R/W
1
Timer/Counter Block Reset Control
1
IC
R/W
1
Interrupt Controller Block Reset Control
0
DAI
R/W
1
DAI/CDIF Block Reset Control
Miscellaneous block contains ADC, Leading Zero Counter register, and other system configuration registers.
Soft reset for this block is not recommended.
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