TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
CLOCK GENERATOR
Preliminary
8-10
EX1CLK Control Register (EX1CLKmode)
0x80000414
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIVX1
EX1_PHASE[13:0]
Bit
Name
Type Default Description
31:16 Reserved
R
0
Reserved
15:14 DIVX1
R/W
0
EX1CLK Divisor Clock Select
DIVX1
fDIVX1 (Divisor Clock Source Selected)
0
XIN input
1
PLL output
2
XTIN input
3
PLLDIVCLK (PLL clock divider output)
13:0 EX1_PHASE R/W
0
EX1CLK Clock Frequency Select
DIVMODE[6]
EX1_PHASE
fEX1CLK (EX1CLK Frequency)
0
0
fDIVX1
0
1 ~ 0x2000
fDIVX1 * EX1_PHASE / 2
14
0
> 0x2000
Undefined. Do not use.
1
X
fDIVX1 / (EX1_PHASE + 1)
EX1CLK is also controlled by EX1 bit of CKCTRL register that can enable or disable EX1CLK. If this bit is set to
high, EX1CLK is disabled and if it is low, EX1CLK is enabled.
External clock is user-programmable clock that can be used various purposes. It is not used by internal peripherals, and
by setting GPIO registers, GPIO_B29, GPIO_B24 and GPIO_B[5:2] pins can output this clock to user application
board. Care must be taken not to use too high frequency that these pins cannot cope with.
UTCLK (UART) Control Register (UTCLKmode)
0x80000418
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIVUT
UT_PHASE[13:0]
Bit
Name
Type Default Description
31:16 Reserved
R
0
Reserved
15:14 DIVUT
R/W
0
UTCLK Divisor Clock Select
DIVUT fDIVUT (Divisor Clock Source Selected)
0
XIN input
1
PLL output
2
XTIN input
3
PLLDIVCLK (PLL clock divider output)
13:0 UT_PHASE
R/W
0x1BE UTCLK Clock Frequency Select
DIVMODE[7]
UT_PHASE
fUTCLK (UTCLK Frequency)
0
0
fDIVUT
0
1 ~ 0x2000
fDIVUT * UT_PHASE / 2
14
0
> 0x2000
Undefined. Do not use.
1
X
fDIVUT / (UT_PHASE + 1)
UTCLK is also controlled by UART bit of CKCTRL register that can enable or disable UTCLK. If this bit is set to
high, UTCLK is disabled and if it is low, UTCLK is enabled
This clock is used by UART. For reliable communication with host side, this clock has the frequency of 3.6864MHz
or so. The UART clock is then divided by DL register in UART block, it is not so important to maintain the duty ratio
of 50%.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
