TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
CLOCK GENERATOR
Preliminary
8-11
UBCLK (USB) Control Register (UBCLKmode)
0x8000041C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
DIVUB
0
UB_PHASE[5:0]
UBCLK is used as the main clock of both USB Host and Device block.
Bit
Name
Type Default Description
31:10 Reserved
R
0
Reserved
9:8
DIVUB
R/W
0
UBCLK Divisor Clock Select
DIVUB fDIVUB (Divisor Clock Source Selected)
0
XIN input
1
PLL output
2
XTIN input
3
PLLDIVCLK (PLL clock divider output)
7:6
Reserved
R
0
Reserved
5:0
UB_PHASE
R/W
0
UBCLK Clock Frequency Select
DIVMODE[8]
UB_PHASE
fUBCLK (UBCLK Frequency)
0
0
fDIVUB
0
1 ~ 0x20
fDIVUB * UB_PHASE / 2
6
0
> 0x20
Undefined. Do not use.
1
X
fDIVUB / (UB_PHASE + 1)
UBCLK is gated separately by “UBH” bit and “USB” bit of CKCTRL register to generate UHCLK (for Host
Controller) and UDCLK (for Device Controller).
LCLK (LCD) Control Register (LCLKmode)
0x80000420
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
DIVLCD
0
LCD_PHASE[5:0]
Bit
Name
Type Default Description
31:10 Reserved
R
0
Reserved
9:8
DIVLCD
R/W
0
LCLK Divisor Clock Select
DIVLCD fDIVLCD (Divisor Clock Source Selected)
0
XIN input
1
PLL output
2
XTIN input
3
PLLDIVCLK (PLL clock divider output)
7:6
Reserved
R
0
Reserved
5:0
LCD_PHASE R/W
0
LCLK Clock Frequency Select
DIVMODE[9]
LCD_PHASE fLCLK (LCLK Frequency)
0
0
fDIVLCD
0
1 ~ 0x20
fDIVLCD * LCD_PHASE / 2
6
0
> 0x20
Undefined. Do not use.
1
X
fDIVLCD / (LCD_PHASE + 1)
LCLK is also controlled by LCK bit of CKCTRL register that can enable or disable LCLK. If this bit is set to high,
LCLK is disabled and if it is low, LCLK is enabled.
To avoid LCD FIFO underrun, LCLK frequency must be set below HCLK frequency.
fLCD < fHCLK
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