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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
USB CONTROLLER
Preliminary
9-5
These registers act as status registers when interrupt is generated. Once interrupt
generated, it is needed to read all the interrupt registers and write back to all the registers
to clear the interrupt. The endpoint interrupt register UBEIR has three bit fields that
correspond to the respective endpoints.
The EP0 interrupt is generated under the following conditions:
•
OUT Packet is ready. ORDY field is set in the of EP0 CSR register.
•
IN Packet is ready. IRDY field is set in the of EP0 CSR register.
•
STST (STALL Handshake Issued) flag is set.
•
CEND (Control Transfer End) flag is set.
•
DEND (Data Transfer End) is cleared (Indicates End of control transfer).
The EP1/E2 interrupt is generated under the following conditions:
For IN endpoints
•
IRDY field is cleared in its CSR register.
•
FIFO is flushed
•
STST (STALL Handshake Issued) flag is set
•
For OUT endpoints
•
ORDY field is set in its CSR register.
•
STST (STALL Handshake Issued) flag is set
For ISO IN endpoints:
UNDER_RUN bit is set
IRDY field is cleared in its CSR register.
FIFO is flushed
For ISO OUT endpoints:
ORDY field is set in its CSR register
OVER RUN bit is set.
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