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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
MISCELLANEOUS PERIPHERALS
Preliminary
12-2
12.1.2 ADC Controller Register Description
Table 12.1 ADC Controller Register Map (Base Address = 0x80000A00)
Name
Address
Type
Reset
Description
ADCCON
0x00
R/W
0x00000018
ADC Control Register
ADCDATA
0x04
R
Unknown
ADC Data Register
ADCCONA
0x80
R/W
0x00000018
ADC Control Register A
ADCSTATUS
0x84
R/W
Unknown
ADC Status Register
ADCCFG
0x88
R/W
0x00002400
ADC Configuration Register
•
ADCCON and ADCDATA registers are preserved for the TCC72x compatibility. For the new features in
the TCC76x, ADCCONA and ADCSTATUS registers should be accessed.
ADC Control Register (ADCCON)
0x80000A00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
STB
X
ASEL
STB [4]
Type
ADC Standby Select
1
ADC goes to standby mode
0
R/W
ADC starts operating
ASEL [2:0]
ADC Input Select
n
ADINn pin is selected as ADC input signal
n = 0 ~ 7 in TCC761.
n = 0, 2, 4 in other derivatives. Refer to Pin Description
ADC Data Register (ADCDATA)
0x80000A04
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
ADATA
FLG
ADATA [10:1]
ADC Data
adc
ADC data = adc
*) All the AD input levels must be within the operable range that is from 0 V to
VDDADC(the main power level of ADC). Do not exceed the limit.
FLG [0]
ADC Status Flag
1
Indicate that A/D conversion has finished, data is stable.
0
A/D conversion is on processing, data is unstable
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