157 / 259 page
TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
MISCELLANEOUS PERIPHERALS
Preliminary
12-5
Miscellaneous Configuration Register (MISCFG)
0x80000A1C
Bit
Name
R/W
Reset Description
31:16
Reserved
R
0
15
RDYIRQEN
R/W
0
READY Interrupt Request Enable.
When enabled, input from
READY pin can generate interrupt to the CPU via channel [15] of
Interrupt Controller. MEN bit of Interrupt Enable Register is used for
interrupt enable bit for READY pin only. Refer to RDY bits in
Section 5.2 Interrupt Controller Register Description.
14
RDYIRQPOL
R/W
0
READY Interrupt Request Polarity Control. (1 = inverted)
13:5
Reserved
R
0
4
CIFEN
R/W
0
Camera Interface Enable on to GPIO pins. CIFEN has a precedence
over CFGI2C bit and GPIO control bits.
Camera Interface Signals
GPIO Pins
HS
GPIO_D[17]
VS
GPIO_D[16]
CLK
GPIO_D[15]
Data[7:4]
GPIO_D[21:18]
Data[3:0]
GPIO_A[3:0]
3:2
Reserved
R
0
1:0
CFGI2C
R/W
0
These bits selects GPIO pins for I2C signals.
CIFEN
CFGI2C[1:0]
SCL
SDA
X
00
Disabled
Disabled
X
01
GPIO_A[9]
GPIO_A[8]
X
10
GPIO_A[11]
GPIO_A[10]
0
11
GPIO_D[17]
GPIO_D[16]
1
11
Disabled
Disabled
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
