TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
MISCELLANEOUS PERIPHERALS
Preliminary
12-3
ADC Control Register A (ADCCONA)
0x80000A80
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
STB
X
ASEL
*) This register has the same functionality as that of ADCCON register. Only the register address is different.
ADC Status Register (ADCSTATUS)
0x80000A84
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
WBVCNT
R
RBVCNT
Reserved
RSELV
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
RBDATA
Bit
Name
R/W Reset Description
31
Reserved
R
0
30:28 WBVCNT
R
0
Command Write Buffer Valid entry count. Up to 4 entries
with different ASEL values can be posted to command buffer.
27
Reserved
R
0
26:24
RBVCNT
R
0
Read Data Buffer Valid entry count. Up to 4 entries.
23:19
Reserved
R
0
18:16
RSEL
R
X
Input channel number for current read data. Valid only if RBCNT
is not zero.
15:10
Reserved
R
0
9:0
RBDATA
R
X
Read Buffer Data.
ADC Configuration Register (ADCCFG)
0x80000A88
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLKDIV
DLYSTC
NEOC
0
FIFOTH
IRQE
R8
APD
SM
Bit
Name
R/W Reset Description
15:12
CLKDIV
R/W
0x2
Clock Divisor Value. ADCLK is divided by ((CLKDIV + 1) * 2).
11:8
DLYSTC
R/W
0x4
Delay from SEL to STC (Start of Conversion) in ADC core CLK
count. Whenever SEL value changes, delay is inserted.
7
NEOC
R/W
0
For test purpose only. Must be written as “0”
6
Reserved
R/W
0
5:4
FIFOTH
R/W
0
FIFO Threshold for interrupt assertion. Interrupt will be asserted
only if FIFOTH < (# of Valid Entry).
3
IRQE
R/W
0
Interrupt Enable.
2
R8
R/W
0
When this bit is “1”, two LSBs are truncated. (shift right). Only
“ADCSTATUS” register is affected by this bit.
1
APD
R/W
0
Auto Power Down Enable. This bit is effective only if SM bit
(described below) is “1”. After conversion cycle is done, the ADC
core is forced to power down mode.
0
SM
R/W
0
Single Mode Enable. When disabled (0), ADC conversion cycle
is repeated forever with the input selected by ASEL bits. When
enabled (1), only one cycle is executed.
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