TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
BOOTING PROCEDURE
Preliminary
20-2
Table 20.1 Booting Mode of the TCC76x
BM[2:0]
Description
x1x
F/W download from USB interface
If one of other boot processing (except external boot) fails, it starts this
boot procedure automatically.
001
I2C or NAND boot
I2C interface using GPIO_D17 as I2C clock and GPIO_D16 as I2C
data. NAND chip enable is controlled either by GPIO_A7 or A6 or D13
or D12, and NAND out-enable is controlled by nCS2.
It can be used to attach serial EEPROM acquiring another function, or
can remove NOR flash by put the F/W code in NAND flash.
100
NOR boot, F/W download from USB I/F.
NOR must be attached to nCS3 pin, and bus width can be configured
by GPIO_A[9:8]. NOR can contain encrypted code or normal code.
If NOR code is corrupted, the TCC76x automatically changes to USB
boot mode so user can fix NOR contents via USB interface.
101
Development mode
JTAG and SDRAM are enabled, and the base address of SDRAM is
remained. The TCC76x is waiting for JTAG connection while toggling
the GPIO_A[0] output.
000
NOR boot without encryption
NOR flash must be attached to nCS3 pin.
In the TCC760 and TCC761 the NOR flash is externally attached to
nCS3. In the other TCC76x derivatives with on chip NOR flash, the
nCS3 must be externally connected to FCSN pin.
20.2 External ROM Boot without Encryption (BM == 000)
It supports an external boot ROM.
When external boot mode, the sequence begins from external ROM that is attached to
nCS3.
The bus width of external boot ROM can be determined by state of GPIO_A[9:8] at the
rising edge of nRESET pin. If GPIO_A[9:8] == 0, the bus width is 16bit, if GPIO_A[9:8]
== 1, it is 8bit, otherwise, it is 32bit. (Refer to the chapter of memory controller for more
details)
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