RA2L2 datasheet(4/108 Pages) RENESAS

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Table 1.6

Timers (2 of 2)

Feature

Functional description

Low Power Asynchronous General

Purpose Timer (AGTW)

The Low Power Asynchronous General Purpose Timer (AGTW) is a 32-bit timer that can be

used for pulse output, external pulse width or period measurement, and counting external

events. This timer consists of a reload register and a down counter. The reload register and

the down counter are allocated to the same address, and can be accessed with the AGTW

Realtime Clock (RTC)

The RTC has two operation modes, normal operation mode and low-consumption clock mode. In

each of the operation mode, the RTC has two counting modes, calendar count mode and binary

count mode, that are used by switching register settings. For calendar count mode, the RTC

has a 100-year calendar from 2000 to 2099 and automatically adjusts dates for leap years. For

binary count mode, the RTC counts seconds and retains the information as a serial value. Binary

count mode can be used for calendars other than the Gregorian (Western) calendar.

Table 1.7

Communication interfaces

Feature

Functional description

Serial Communications Interface (SCI)

The Serial Communications Interface (SCI) × 4 channels have asynchronous and synchronous

serial interfaces:

● Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter

(ACIA))

● 8-bit clock synchronous interface

● Simple IIC (master-only)

● Simple SPI

● Smart card interface

The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and

transmission protocol. SCIn (n = 0) has FIFO buffers to enable continuous and full-duplex

communication, and the data transfer speed can be configured independently using an on-chip

baud rate generator.

I3C bus interface (I3C)

The I3C bus interface (I3C) has one channel. The I3C module conform with and provide a

subset of the NXP I2C (Inter-Integrated Circuit) bus interface functions and a subset of the MIPI

I3C.

Serial Peripheral Interface (SPI)

The Serial Peripheral Interface (SPI) has 1 channel. The SPI provides high-speed full-duplex

synchronous serial communications with multiple processors and peripheral devices.

Control Area Network (CAN)

The Controller Area Network (CAN) module uses a message-based protocol to receive and

transmit data between multiple slaves and masters in electromagnetically noisy applications. The

module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports up to 32

mailboxes, which can be configured for transmission or reception in normal mailbox and FIFO

modes. Both standard (11-bit) and extended (29-bit) messaging formats are supported. The CAN

module requires an additional external CAN transceiver.

USB 2.0 Full-Speed (USBFS) module

The USB 2.0 Full-Speed (USBFS) module can operate as a device controller.

The module supports full-speed transfer as defined in Universal Serial Bus Specification 2.0.

The module has an internal USB transceiver and supports all of the transfer types defined in

Universal Serial Bus Specification 2.0. The USB has buffer memory for data transfer, providing

a maximum of 10 pipes. Pipes 1 to 9 can be assigned any endpoint number based on the

peripheral devices used for communication or based on your system.

USB Type-C interface (USBCC)

The module supports for USB Type-C connector of USB 2.0 (Sink/UFP only) as defined in

Universal Serial Bus Type-C Cable and Connector Specification Release 2.2, and the module

can detect the current supply capability (default /1.5A/3.0A) of VBUS.

Serial interface UARTA (UARTA)

The serial interface UARTA (UARTA) has 2 channels. The UARTA provides full-duplex

asynchronous serial communications.

Serial Sound Interface Enhanced (SSIE) The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface with

digital audio devices for transmitting I2S/Monaural/TDM audio data over a serial bus. The SSIE

supports an audio clock frequency of up to 32 MHz, and can be operated as a slave or master

receiver, transmitter, or transceiver to suit various applications. The SSIE includes 32-stage FIFO

buffers in the receiver and transmitter, and supports interrupts and DTC-driven data reception

and transmission.

RA2L2 Datasheet

1. Overview

R01DS0445EJ0120 Rev.1.20

Jun 9, 2026

Page 4 of 108

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