RA2L2 datasheet(85/108 Pages) RENESAS

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Table 2.56

Power-on reset circuit and voltage detection circuit characteristics (2) (2 of 2)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Power-on reset enable time

tW (POR)

—

Figure 2.58, VCC = below 1.0

LVD1 operation stabilization time (after LVD1 is

enabled)

Td (E-A)

—

300

µs

Figure 2.60

LVD2 operation stabilization time (after LVD2 is

enabled)

Td (E-A)

—

1200

µs

Figure 2.61

Hysteresis width (POR)

VPORH

—

Hysteresis width (LVD0, LVD1 and LVD2)

VLVH

—

LVD0 selected

—

110

—

Vdet1_0 to Vdet1_2 selected

—

Vdet1_3 to Vdet1_9 selected

—

Vdet1_A to Vdet1_B selected

—

Vdet1_C to Vdet1_F selected

—

LVD2 selected

Note 1. When OFS1.LVDAS = 0.

Note 2. When OFS1.LVDAS = 1.

Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet0,

Vdet1, and Vdet2 for the POR/LVD.

Internal reset signal

(active-low)

VCC

tVOFF

tPOR

tdet

VPOR

tdet

1.0 V

Figure 2.57

Voltage detection reset timing

RA2L2 Datasheet

2. Electrical Characteristics

R01DS0445EJ0120 Rev.1.20

Jun 9, 2026

Page 85 of 108

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