RA2L2 datasheet(46/108 Pages) RENESAS

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Table 2.31

SCI timing (2) (1 of 2)

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

Min

Max

Unit*1

Test

conditions

Simple

SPI

SCK clock cycle output

(master)

2.7 V ≤ VCC ≤ 5.5 V

tSPcyc

125

—

Figure 2.22

2.4 V ≤ VCC < 2.7 V

250

—

1.8 V ≤ VCC < 2.4 V

500

—

1.6 V ≤ VCC < 1.8 V

1000

—

SCK clock cycle input

(slave)

2.7 V ≤ VCC ≤ 5.5 V

187.5

—

2.4 V ≤ VCC < 2.7 V

375

—

1.8 V ≤ VCC < 2.4 V

750

—

1.6 V ≤ VCC < 1.8 V

1500

—

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise and fall

time

1.8 V ≤ VCC ≤ 5.5 V

tSPCKr,

tSPCKf

—

1.6 V ≤ VCC < 1.8 V

—

Data input

setup time

Master

2.7 V ≤ VCC ≤ 5.5 V

tSU

—

Figure 2.23 to

Figure 2.26

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

110

—

Slave

2.7 V ≤ VCC ≤ 5.5 V

—

1.6 V ≤ VCC < 2.7 V

—

Data input

hold time

Master

33.3

—

Slave

—

SS input setup time

tLEAD

—

tSPcyc

SS input hold time

tLAG

—

tSPcyc

Data output

delay time

Master

1.8 V ≤ VCC ≤ 5.5 V

tOD

—

1.6 V ≤ VCC < 1.8 V

—

Slave

2.4 V ≤ VCC ≤ 5.5 V

—

1.8 V ≤ VCC < 2.4 V

—

100

1.6 V ≤ VCC < 1.8 V

—

125

Data output

hold time

Master

2.7 V ≤ VCC ≤ 5.5 V

tOH

-10

—

2.4 V ≤ VCC < 2.7 V

-20

—

1.8 V ≤ VCC < 2.4 V

-30

—

1.6 V ≤ VCC < 1.8 V

-40

—

Slave

-10

—

Data rise and

fall time

Master

1.8 V ≤ VCC ≤ 5.5 V

tDr, tDf

—

1.6 V ≤ VCC < 1.8 V

—

Slave

1.8 V ≤ VCC ≤ 5.5 V

—

1.6 V ≤ VCC < 1.8 V

—

RA2L2 Datasheet

2. Electrical Characteristics

R01DS0445EJ0120 Rev.1.20

Jun 9, 2026

Page 46 of 108

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