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RA2L2 Datasheet(PDF) 57 Page - Renesas Technology Corp |
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RA2L2 Datasheet(HTML) 57 Page - Renesas Technology Corp |
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57 / 108 page  2.3.10 I3C Timing Table 2.34 IIC timing Conditions: VCC = 2.7 to 5.5 V Parameter Symbol Min*1 Max Unit Test conditions IIC (standard mode, SMBus) SCL cycle time tSCL 6 (40) × tIICcyc + 4 × tPcyc + 1300 — ns Figure 2.35 SCL high pulse width tSCLH 3 (20) × tIICcyc + 2 × tPcyc + 300 — ns SCL low pulse width tSCLL 3 (20) × tIICcyc + 2 × tPcyc + 800 — ns SCL, SDA rise time tSr — 1000 ns SCL, SDA fall time tSf — 300 ns SCL, SDA spike pulse removal time tSP 0 1 (16) × tIICcyc ns SDA bus free time tBUF 3 (20) × tIICcyc + 300 — ns Hold time for START condition tSTAH tIICcyc + 300 — ns Setup time for repeated START condition tSTAS 1000 — ns Setup time for STOP condition tSTOS 1000 — ns Data setup time tSDAS tIICcyc + 50 — ns Data hold time tSDAH 0 — ns SCL, SDA capacitive load Cb — 400 pF IIC (Fast mode) SCL cycle time tSCL 6 (40) × tIICcyc + 4 × tPcyc + 600 — ns Figure 2.35 SCL high pulse width tSCLH 3 (20) × tIICcyc + 2 × tPcyc + 300 — ns SCL low pulse width tSCLL 3 (20) × tIICcyc + 2 × tPcyc + 300 — ns SCL, SDA rise time tSr — 300 ns SCL, SDA fall time tSf — 300 ns SCL, SDA spike pulse removal time tSP 0 1 (16) × tIICcyc ns SDA bus free time tBUF 3 (20) × tIICcyc + 300 — ns Hold time for START condition tSTAH tIICcyc + 300 — ns Setup time for repeated START condition tSTAS 300 — ns Setup time for STOP condition tSTOS 300 — ns Data setup time tSDAS tIICcyc + 50 — ns Data hold time tSDAH 0 — ns SCL, SDA capacitive load Cb — 400 pF Note: tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKD cycle Note 1. Values in parentheses apply when INCTL.DNFS[3:0] is set to 1111b while the digital filter is enabled with DNFE.DNFE set to 1. RA2L2 Datasheet 2. Electrical Characteristics R01DS0445EJ0120 Rev.1.20 Jun 9, 2026 Page 57 of 108 |
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