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RA2L2 Datasheet(PDF) 71 Page - Renesas Technology Corp |
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RA2L2 Datasheet(HTML) 71 Page - Renesas Technology Corp |
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71 / 108 page ![]() tDTRW SSILRCK0/SSIFS0 (input) SSITXD0 (output) MSB bit output delay after SSILRCK0/SSIFS0 change for slave transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0] = DWL[2:0] in SSICR. Figure 2.49 SSIE data output delay after SSILRCK0/SSIFS0 change 2.3.12 UARTA Timing Table 2.40 UARTA interface timing Parameter Symbol Min. Max. Unit Test conditions Transfer rate — 200 153600 bps — 2.3.13 CLKOUT Timing Table 2.41 CLKOUT timing Parameter Symbol Min Max Unit Test conditions CLKOUT CLKOUT pin output cycle*1 2.7 V ≤ VCC ≤ 5.5 V tCcyc 62.5 — ns Figure 2.50 1.8 V ≤ VCC < 2.7 V 125 — 1.6 V ≤ VCC < 1.8 V 250 — CLKOUT pin high pulse width*2 2.7 V ≤ VCC ≤ 5.5 V tCH 15 — ns 1.8 V ≤ VCC < 2.7 V 30 — 1.6 V ≤ VCC < 1.8 V 150 — CLKOUT pin low pulse width*2 2.7 V ≤ VCC ≤ 5.5 V tCL 15 — ns 1.8 V ≤ VCC < 2.7 V 30 — 1.6 V ≤ VCC < 1.8 V 150 — CLKOUT pin output rise time 2.7 V ≤ VCC ≤ 5.5 V tCr — 12 ns 1.8 V ≤ VCC < 2.7 V — 25 1.6 V ≤ VCC < 1.8 V — 50 CLKOUT pin output fall time 2.7 V ≤ VCC ≤ 5.5 V tCf — 12 ns 1.8 V ≤ VCC < 2.7 V — 25 1.6 V ≤ VCC < 1.8 V — 50 Note 1. When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, specifications in Table 2.41 should be satisfied with 45% to 55% of input duty cycle. Note 2. When MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division ratio to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b). RA2L2 Datasheet 2. Electrical Characteristics R01DS0445EJ0120 Rev.1.20 Jun 9, 2026 Page 71 of 108 |
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