RA2L2 datasheet(60/108 Pages) RENESAS

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SDAn

SCLn

VIH

VIL

tSTAH

tSCLH

tSCLL

P*1

S*1

tSf

tSr

tSCL

tSDAH

tSDAS

tSTAS

tSP

tSTOS

P*1

tBUF

Sr*1

Note:

n = 0

Note 1. S, P, and Sr indicate the following conditions:

S: Start condition

P: Stop condition

Sr: Restart condition

Figure 2.35

I2C bus interface input/output timing

Table 2.37

I3C timing (Open Drain Timing Parameters)

Conditions: VCC = 2.97 to 3.63 V

Parameter

Symbol

Timing Diagram Min

Max

Units

Notes

SCL Clock Low Period

tLOW_OD

Figure 2.38

200

—

1, 2

tDIG_OD_L Figure 2.38

tLOW_ODmin +

tfDA_ODmin

—

SDA Signal Fall Time

tfDA_OD

Figure 2.38

tCF

—

SDA Data Setup Time Open Drain Mode

tSU_OD

Figure 2.37

—

Figure 2.38

Clock After START (S) Condition

tCAS

Figure 2.38

38.4

For ENTAS0: 1 μ

seconds 5, 6

For ENTAS1: 100 μ

For ENTAS2: 2 m

For ENTAS3: 50 m

Clock Before STOP (P) Condition

tCBP

Figure 2.39

tCASmin

—

seconds —

Current Master to Secondary Master

Overlap time during handoff

tMMOverlap Figure 2.44

tDIG_OD_Lmin

—

Bus Available Condition

tAVAL

—

μs

Bus Idle Condition

tIDLE

—

Time Internal Where New Master Not

Driving SDA Low

tMMLock

Figure 2.44

tAVALmin

—

μs

—

Note:

1. This is approximately equal to tLOWmin + tDS_ODmin + trDA_ODtyp + tSU_ODmin.

2. The Master may use a shorter Low period if it knows that this is safe, i.e., that SDA is already above VIH.

3. On a Legacy Bus where I2C Devices need to see Start.

4. Slaves that do not support the optional ENTASx CCCs shall use the tCAS Max value shown for ENTAS3

5. On a Mixed Bus with Fm Legacy I2C Devices, tAVAL is 300 ns shorter than the Fm Bus Free Condition time (tBUF)

RA2L2 Datasheet

2. Electrical Characteristics

R01DS0445EJ0120 Rev.1.20

Jun 9, 2026

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