RA2L2 datasheet(44/108 Pages) RENESAS

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2.3.8

SCI Timing

Table 2.30

SCI timing (1)

Conditions: VCC = AVCC0 = 1.6 to 5.5 V

Parameter

Symbol

Min

Max

Unit

Test

conditions

SCI

Input clock cycle

Asynchronous

2.7 V ≤ VCC ≤ 5.5 V

tScyc

125

—

Figure 2.20

2.4 V ≤ VCC < 2.7 V

250

—

1.8 V ≤ VCC < 2.4 V

500

—

1.6 V ≤ VCC < 1.8 V

1000

—

Clock

synchronous

2.7 V ≤ VCC ≤ 5.5 V

187.5

—

2.4 V ≤ VCC < 2.7 V

375

—

1.8 V ≤ VCC < 2.4 V

750

—

1.6 V ≤ VCC < 1.8 V

1500

—

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Input clock rise time

tSCKr

—

Input clock fall time

tSCKf

—

Output clock cycle

Asynchronous

2.7 V ≤ VCC ≤ 5.5 V

tScyc

187.5

—

2.4 V ≤ VCC < 2.7 V

375

—

1.8 V ≤ VCC < 2.4 V

750

—

1.6 V ≤ VCC < 1.8 V

1500

—

Clock

synchronous

2.7 V ≤ VCC ≤ 5.5 V

125

—

2.4 V ≤ VCC < 2.7 V

250

—

1.8 V ≤ VCC < 2.4 V

500

—

1.6 V ≤ VCC < 1.8 V

1000

—

Output clock pulse width

tSCKW

0.4

0.6

tScyc

Output clock rise time

1.8 V ≤ VCC ≤ 5.5 V

tSCKr

—

1.6 V ≤ VCC < 1.8 V

—

Output clock fall time

1.8 V ≤ VCC ≤ 5.5 V

tSCKf

—

1.6 V ≤ VCC < 1.8 V

—

Transmit data delay

time (master)

Clock

synchronous

1.8 V ≤ VCC ≤ 5.5 V

tTXD

—

Figure 2.21

1.6 V ≤ VCC < 1.8 V

—

Transmit data delay

time (slave)

Clock

synchronous

2.7 V ≤ VCC ≤ 5.5 V

—

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

100

1.6 V ≤ VCC < 1.8 V

—

125

Receive data setup

time (master)

Clock

synchronous

2.7 V ≤ VCC ≤ 5.5 V

tRXS

—

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC < 2.4 V

—

1.6 V ≤ VCC < 1.8 V

110

—

Receive data setup

time (slave)

Clock

synchronous

2.7 V ≤ VCC ≤ 5.5 V

—

1.6 V ≤ VCC < 2.7 V

—

Receive data hold

time (master)

Clock synchronous

tRXH

—

Receive data hold

time (slave)

Clock synchronous

tRXH

—

RA2L2 Datasheet

2. Electrical Characteristics

R01DS0445EJ0120 Rev.1.20

Jun 9, 2026

Page 44 of 108

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