RA2L2 datasheet(69/108 Pages) RENESAS

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Table 2.39

SSIE timing (2 of 2)

Conditions: VCC = 2.7 to 5.5 V

(1) Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership. For the SSIE interface, the

AC portion of the electrical characteristics is measured for each group.

Parameter

Symbol

Target specification

Unit

Test conditions

Min

Max

SSILRCK0/

SSIFS0,

SSITXD0,

SSIRXD0

Input set up time

Master

tSR

—

Figure 2.47,

Figure 2.48

Slave

—

Input hold time

Master

tHR

—

Slave

—

Output delay time

Master

tDTR

Slave

Output delay time

from SSILRCK0/ SSIFS0

change

Slave

tDTRW

Figure 2.47,

Figure 2.48

GTIOC4A,

AUDIO_CLK

Cycle

tEXcyc

31.25

—

Figure 2.46

High level/ Low level

tEXL/tEXH

0.4

0.6

tEXcyc

SSIBCK0

tHC

tO, tI

tLC

tRC

tFC

Figure 2.45

SSIE clock input/output timing

GTIOC4A,

AUDIO_CLK

(input)

tEXH

tEXL

tEXr

tEXcyc

tEXf

1/2 VCC

Figure 2.46

Clock input timing

RA2L2 Datasheet

2. Electrical Characteristics

R01DS0445EJ0120 Rev.1.20

Jun 9, 2026

Page 69 of 108

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