WM8959 datasheet(104/155 Pages) WOLFSON

104 / 155 page

WM8959

Pre-Production

PP, May 2008, Rev 3.1

104

CLOCKING AND SAMPLE RATES

The internal clocks for the DACs, DSP core functions, digital audio interface and Class D switching

amplifier are all derived from a common internal clock source, SYSCLK.

SYSCLK can either be derived directly from MCLK, or may be generated from a PLL using MCLK as

an external reference. Many commonly-used audio sample rates can be derived directly from typical

MCLK frequencies; the PLL provides additional flexibility for a wide range of MCLK frequencies. All

clock configurations must be set up before enabling playback to avoid glitches.

The DAC sample rate is selectable, relative to SYSCLK by setting register field DAC_CLKDIV. This

field must be set according to the required sampling frequency and depending on the selected

clocking mode (AIF_LRCLKRATE).

In master mode, BCLK is also derived from SYSCLK via a programmable division set by BCLK_DIV.

The DACLRC signal does not automatically match the DAC sample rates; this must be configured

using DACLRC_RATE as described under “Digital Audio Interface Control”.

A clock (OPCLK) derived from SYSCLK can be output on the GPIO pins to provide clocking for other

parts of the system. This clock is enabled by OPCLK_ENA and its frequency is set by OPCLKDIV.

A slow clock (TOCLK) derived from SYSCLK can be used to de-bounce the button/accessory detect

inputs, and to set the timeout period for volume updates when zero-cross detect is used. This clock

is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE.

The Class D switching amplifier requires a clock; this is derived from SYSCLK via a programmable

divider DCLKDIV.

Table 56 to Table 62 show the clocking and sample rate controls for MCLK input, BCLK output (in

master mode), DACs, class D outputs and GPIO clock output.

The overall clocking scheme for the WM8959 is illustrated in Figure 78.

MCLK

PLL

R=f2/f1

SYSCLK

DAC

MASTER

MODE

CLOCK

OUTPUTS

fPLLOUT

f/N

256fs

f/N

f/4

f/2

f/N

GPIO Clock Output

f/N

Class D Switching Clock

Timeout and

De-Bounce

Clock

Button/accessory detect de-bounce,

Volume update timeout

TOCLK_ENA

f/221

f/2

SYSCLK

All internal clocks are derived from SYSCLK.

SYSCLK can be derived directly from MCLK or from the PLL output and has a

programmable divide by 2 option (MCLKDIV).

DAC_CLKDIV

DAC sample rate is set by DAC_CLKDIV (Master or slave mode).

DACLRC_RATE

DACLRC in master mode is derived from BCLK and is controlled by DACLRC_RATE.

BCLK_DIV

BCLK rate is set by BCLK_DIV in master mode.

OPCLKDIV

GPIO Clock output frequency is set by OPCLKDIV.

DCLKDIV

Class D switching clock frequency is set by DCLKDIV and should be between 700kHz

and 800kHz for best performance.

TOCLK_RATE

A slow clock is used for button/accessory detect de-bounce and for volume update

timeouts (when zero-cross detect is enabled). The frequency of this slow clock is set by

TOCLK_RATE.

Other Sample Rate Controls

DEEMP configures the de-emphasis filter for the chosen sample rate.

TOCLK_RATE

DCLKDIV

DCLKDIV[2:0]

000 = SYSCLK

001 = SYSCLK / 2

010 = SYSCLK / 3

011 = SYSCLK / 4

100 = SYSCLK / 6

101 = SYSCLK / 8

110 = SYSCLK / 12

111 = SYSCLK / 16

BCLK_DIV[3:0]

0000 = SYSCLK

0001 = SYSCLK / 1.5

0010 = SYSCLK / 2

0011 = SYSCLK / 3

0100 = SYSCLK / 4

0101 = SYSCLK / 5.5

0110 = SYSCLK / 6

0111 = SYSCLK / 8

1000 = SYSCLK / 11

1001 = SYSCLK / 12

1010 = SYSCLK / 16

1011 = SYSCLK / 22

1100 = SYSCLK / 24

1101 = SYSCLK / 32

1110 = SYSCLK / 44

1111 = SYSCLK / 48

BCLKDIV

[3:0]

OPCLKDIV[3:0]

0000 = SYSCLK

0001 = SYSCLK / 2

0010 = SYSCLK / 3

0011 = SYSCLK / 4

0100 = SYSCLK / 5.5

0101 = SYSCLK / 6

0110 = SYSCLK / 8

0111 = SYSCLK / 12

1000 = SYSCLK /16

1001 – 1111 = Reserved

OPCLKDIV

DAC_CLKDIV2:0]

000 = SYSCLK

001 = SYSCLK / 1.5

010 = SYSCLK / 2

011 = SYSCLK / 3

100 = SYSCLK / 4

101 = SYSCLK / 5.5

110 = SYSCLK / 6

111 = Reserved

DAC_CLKDIV

[2:0]

MCLKDIV[1:0]

00 = MCLK

01 = Reserved

10 = MCLK / 2

11 = Reserved

MCLKDIV[1:0]

SYSCLK_SRC

PRESCALE

OPCLK_ENA

BCLK, BCLK2

DACLRC, DACLRC2

f/N

DACLRC_RATE

[10:0]

MCLK_INV

f/4

DAC_SDMCLK_RATE

DAC DSP

64fs or

SYSCLK/4

Figure 78 Clocking Scheme

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