WM8959 datasheet(105/155 Pages) WOLFSON

105 / 155 page

Pre-Production

WM8959

PP, May 2008, Rev 3.1

105

SYSCLK CONTROL

MCLK may be inverted by setting register bit MCLK_INV. Note that it is not recommended to change

the control bit MCLK_INV while the WM8959 is processing data as this may lead to clock glitches

and signal pop and clicks.

The SYSCLK_SRC bit is used to select the source for SYSCLK. The source may be either MCLK or

the PLL output. The selected source is divided by the SYSCLK pre-divider MCLK_DIV to generate

SYSCLK. The selected source may also be adjusted by the MCLK_DIV divider. These register fields

are described in Table 56. See “PLL” for more details of the Phase Locked Loop clock generator.

The WM8959 supports glitch-free SYSCLK source selection. When both clock sources are running

and SYSCLK_SRC is modified to select one of these clocks, a glitch-free clock transition will take

place. The de-glitching circuit will ensure that the minimum pulse width will be no less than the pulse

width of the faster of the two clock sources.

When the initial clock source is to be disabled before changing to the new clock source, the

CLK_FORCE bit must also be used to force the clock source transition to take place. In this case,

glitch-free operation cannot be guaranteed.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

SYSCLK_SRC

SYSCLK Source Select

0 = MCLK

1 = PLL output

CLK_FORCE

Forces Clock Source Selection

0 = Existing SYSCLK source (MCLK or

PLL output) must be active when

changing to a new clock source.

1 = Allows existing MCLK source to be

disabled before changing to a new clock

source.

12:11

MCLK_DIV

[1:0]

00b

SYSCLK Pre-divider. Clock source

(MCLK or PLL output) will be divided by

this value to generate SYSCLK.

00 = Divide SYSCLK by 1

01 = Reserved

10 = Divide SYSCLK by 2

11 = Reserved

R7 (07h)

MCLK_INV

MCLK Invert

0 = Master clock not inverted

1 = Master clock inverted

Table 56 MCLK and SYSCLK Control

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