LFEC10 datasheet(35/163 Pages) LATTICE

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Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for veriﬁcation. The test

access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage

VCCJ and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.

For more details on boundary scan test, please see information regarding additional technical documentation at

the end of this data sheet.

Device Conﬁguration

All LatticeECP/EC devices contain two possible ports that can be used for device conﬁguration. The test access

port (TAP), which supports bit-wide conﬁguration, and the sysCONFIG port that supports both byte-wide and serial

conﬁguration.

The TAP supports both the IEEE Std. 1149.1 Boundary Scan speciﬁcation and the IEEE Std. 1532 In-System Con-

ﬁguration speciﬁcation. The sysCONFIG port is a 20-pin interface with six of the I/Os used as dedicated pins and

the rest being dual-use pins (please refer to TN1053 for more information about using the dual-use pins as general

purpose I/O). There are four conﬁguration options for LatticeECP/EC devices:

Industry standard SPI memories.

Industry standard byte wide ﬂash and ispMACH 4000 for control/addressing.

Conﬁguration from system microprocessor via the conﬁguration bus or TAP.

Industry standard FPGA board memory.

On power-up, the FPGA SRAM is ready to be conﬁgured with the sysCONFIG port active. The IEEE 1149.1 serial

mode can be activated any time after power-up by sending the appropriate command through the TAP port. Once a

conﬁguration port is selected, that port is locked and another conﬁguration port cannot be activated until the next

power-up sequence.

For more information about device conﬁguration, please see the list of technical documentation at the end of this

data sheet.

Internal Logic Analyzer Capability (ispTRACY)

All LatticeECP/EC devices support an internal logic analyzer diagnostic feature. The diagnostic features provide

capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace

memory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at com-

pile time.

For more information about ispTRACY, please see information regarding additional technical documentation at the

end of this data sheet.

External Resistor

LatticeECP/EC devices require a single external, 10K ohm +/- 1% value between the XRES pin and ground.

Device conﬁguration will not be completed if this resistor is missing. There is no boundary scan register on the

external resistor pad.

LFEC10 Datasheet(PDF) 35 Page - Lattice Semiconductor