LFEC10 datasheet(16/163 Pages) LATTICE

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Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Memory Cascading

Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools

cascade memory transparently, based on speciﬁc design inputs.

Single, Dual and Pseudo-Dual Port Modes

Figure 2-15 shows the four basic memory conﬁgurations and their input/output names. In all the sysMEM RAM

modes the input data and address for the ports are registered at the input of the memory array. The output data of

the memory is optionally registered at the output.

Figure 2-15. sysMEM EBR Primitives

The EBR memory supports three forms of write behavior for single port or dual port operation:

Normal – data on the output appears only during read cycle. During a write cycle, the data (at the current

address) does not appear on the output. This mode is supported for all data widths.

Write Through – a copy of the input data appears at the output of the same port during a write cycle. This

mode is supported for all data widths.

Read-Before-Write – when new data is being written, the old content of the address appears at the output.

This mode is supported for x9, x18 and x36 data widths.

Memory Core Reset

The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-

nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A

and Port B, respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associ-

ated resets for both ports are as shown in Figure 2-16.

EBR

AD[12:0]

DI[35:0]

CLK

RST

CS[2:0]

DO[35:0]

Single Port RAM

EBR

True Dual Port RAM

Pseudo-Dual Port RAM

ROM

AD[12:0]

CLK

DO[35:0]

RST

CS[2:0]

EBR

ADA[12:0]

DIA[17:0]

CLKA

CEA

RSTA

WEA

CSA[2:0]

DOA[17:0]

ADB[12:0]

DIB[17:0]

CLKB

CEB

RSTB

WEB

CSB[2:0]

DOB[17:0]

ADW[12:0]

DI[35:0]

CLKW

CEW

ADR[12:0]

DO[35:0]

CER

CLKR

RST

CS[2:0]

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