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LFEC10 Datasheet(PDF) 59 Page - Lattice Semiconductor |
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LFEC10 Datasheet(HTML) 59 Page - Lattice Semiconductor |
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59 / 163 page  3-23 DC and Switching Characteristics Lattice Semiconductor LatticeECP/EC Family Data Sheet sysCLOCK PLL Timing Over Recommended Operating Conditions Parameter Description Conditions Min. Typ. Max. Units fIN Input Clock Frequency (CLKI, CLKFB) 25 — 420 MHz fOUT Output Clock Frequency (CLKOP, CLKOS) 25 — 420 MHz fOUT2 K-Divider Output Frequency (CLKOK) 0.195 — 210 MHz fVCO PLL VCO Frequency 420 — 840 MHz fPFD Phase Detector Input Frequency 25 — — MHz AC Characteristics tDT Output Clock Duty Cycle Default Duty Cycle Elected 3 45 50 55 % tPH 4 Output Phase Accuracy — — 0.05 UI tOPJIT 1 Output Clock Period Jitter fOUT >= 100MHz — — +/- 125 ps fOUT < 100MHz — — 0.02 UIPP tSK Input Clock to Output Clock Skew Divider ratio = integer — — +/- 200 ps tW Output Clock Pulse Width At 90% or 10% 3 1— — ns tLOCK 2 PLL Lock-in Time — — 150 µs tPA Programmable Delay Unit 100 250 450 ps tIPJIT Input Clock Period Jitter — — +/- 200 ps tFBKDLY External Feedback Delay — — 10 ns tHI Input Clock High Time 90% to 90% 0.5 — — ns tLO Input Clock Low Time 10% to 10% 0.5 — — ns tRST RST Pulse Width 10 — — ns 1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock. 2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment. 3. Using LVDS output buffers. 4. Relative to CLKOP. Timing v.G 0.30 |
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