LFEC10 datasheet(25/163 Pages) LATTICE

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Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Table 2-12. PIO Signal List

Figure 2-25. DQS Routing

PIO

The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic

block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along

with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-

nals are also included in these blocks.

Name

Type

Description

CE0, CE1

Control from the core

Clock enables for input and output block FFs.

CLK0, CLK1

Control from the core

System clocks for input and output blocks.

LSR

Control from the core

Local Set/Reset.

GSRN

Control from routing

Global Set/Reset (active low).

INCK

Input to the core

Input to Primary Clock Network or PLL reference inputs.

DQS

Input to PIO

DQS signal from logic (routing) to PIO.

INDD

Input to the core

Unregistered data input to core.

INFF

Input to the core

Registered input on positive edge of the clock (CLK0).

IPOS0, IPOS1

Input to the core

DDRX registered inputs to the core.

ONEG0

Control from the core

Output signals from the core for SDR and DDR operation.

OPOS0,

Control from the core

Output signals from the core for DDR operation

OPOS1 ONEG1

Tristate control from the core

Signals to Tristate Register block for DDR operation.

Tristate control from the core

Tristate signal from the core used in SDR operation.

DDRCLKPOL

Control from clock polarity bus

Controls the polarity of the clock (CLK0) that feed the DDR input block.

PIO A

PIO B

PADA "T"

PADB "C"

PIO B

PIO A

PIO B

PIO A

Assigned

DQS Pin

DQS

sysIO

Buffer

LVDS Pair

PADA "T"

PADB "C"

LVDS Pair

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

PIO A

PIO B

PADA "T"

PADB "C"

LVDS Pair

Delay

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