 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LFEC10 Datasheet(PDF) 52 Page - Lattice Semiconductor |
|
|
|||||||||||||||||||||||||||||
LFEC10 Datasheet(HTML) 52 Page - Lattice Semiconductor |
|
|
52 / 163 page  3-16 DC and Switching Characteristics Lattice Semiconductor LatticeECP/EC Family Data Sheet LatticeECP/EC Internal Switching Characteristics Over Recommended Operating Conditions Parameter Description -5 -4 -3 Units Min. Max. Min. Max. Min. Max. PFU/PFF Logic Mode Timing tLUT4_PFU LUT4 Delay (A to D Inputs to F Output) — 0.25 — 0.31 — 0.36 ns tLUT6_PFU LUT6 Delay (A to D Inputs to OFX Output) — 0.40 — 0.48 — 0.56 ns tLSR_PFU Set/Reset to Output of PFU — 0.81 — 0.98 — 1.14 ns tSUM_PFU Clock to Mux (M0,M1) Input Setup Time 0.12 — 0.14 — 0.16 — ns tHM_PFU Clock to Mux (M0,M1) Input Hold Time -0.05 — -0.06 — -0.06 — ns tSUD_PFU Clock to D Input Setup Time 0.12 — 0.14 — 0.16 — ns tHD_PFU Clock to D Input Hold time -0.03 — -0.03 — -0.04 — ns tCK2Q_PFU Clock to Q Delay, D-type Register Configuration — 0.36 — 0.44 — 0.51 ns tLE2Q_PFU Clock to Q Delay Latch Configuration — 0.48 — 0.58 — 0.68 ns tLD2Q_PFU D to Q Throughput Delay when Latch is Enabled — 0.50 — 0.60 — 0.69 ns PFU Dual Port Memory Mode Timing tCORAM_PFU Clock to Output — 0.36 — 0.44 — 0.51 ns tSUDATA_PFU Data Setup Time -0.20 — -0.24 — -0.28 — ns tHDATA_PFU Data Hold Time 0.26 — 0.31 — 0.36 — ns tSUADDR_PFU Address Setup Time -0.51 — -0.62 — -0.72 — ns tHADDR_PFU Address Hold Time 0.64 — 0.77 — 0.90 — ns tSUWREN_PFU Write/Read Enable Setup Time -0.24 — -0.29 — -0.34 — ns tHWREN_PFU Write/Read Enable Hold Time 0.30 — 0.36 — 0.42 — ns PIC Timing PIO Input/Output Buffer Timing tIN_PIO Input Buffer Delay — 0.56 — 0.67 — 0.78 ns tOUT_PIO Output Buffer Delay — 1.92 — 2.31 — 2.69 ns IOLOGIC Input/Output Timing tSUI_PIO Input Register Setup Time (Data Before Clock) 0.90 — 1.08 — 1.26 — ns tHI_PIO Input Register Hold Time (Data after Clock) 0.62 — 0.74 — 0.87 — ns tCOO_PIO Output Register Clock to Output Delay — 0.33 — 0.40 — 0.46 ns tSUCE_PIO Input Register Clock Enable Setup Time -0.10 — -0.12 — -0.14 — ns tHCE_PIO Input Register Clock Enable Hold Time 0.12 — 0.14 — 0.17 — ns tSULSR_PIO Set/Reset Setup Time 0.18 — 0.21 — 0.25 — ns tHLSR_PIO Set/Reset Hold Time -0.15 — -0.18 — -0.21 — ns EBR Timing tCO_EBR Clock to Output from Address or Data — 3.64 — 4.37 — 5.10 ns tCOO_EBR Clock to Output from EBR output Register — 0.74 — 0.88 — 1.03 ns tSUDATA_EBR Setup Data to EBR Memory -0.29 — -0.35 — -0.41 — ns tHDATA_EBR Hold Data to EBR Memory 0.37 — 0.44 — 0.52 — ns tSUADDR_EBR Setup Address to EBR Memory -0.29 — -0.35 — -0.41 — ns tHADDR_EBR Hold Address to EBR Memory 0.37 — 0.45 — 0.52 — ns tSUWREN_EBR Setup Write/Read Enable to EBR Memory -0.18 — -0.22 — -0.26 — ns tHWREN_EBR Hold Write/Read Enable to EBR Memory 0.23 — 0.28 — 0.33 — ns |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
