LFEC10 datasheet(12/163 Pages) LATTICE

12 / 163 page

2-9

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-8. Per Quadrant Primary Clock Selection

Figure 2-9. Per Quadrant Secondary Clock Selection

Figure 2-10. Slice Clock Selection

sysCLOCK Phase Locked Loops (PLLs)

The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback sig-

nal to the feedback divider: from CLKOP (PLL Internal), from clock net (CLKOP) or from a user clock (PIN or logic).

There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-11 shows the

sysCLOCK PLL diagram.

The setup and hold times of the device can be improved by programming a delay in the feedback or input path of

the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-

4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant

20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing1

DCS

1. Smaller devices have fewer PLL related lines.

4 Secondary Clocks per Quadrant

20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals

Primary Clock

Secondary Clock

Routing

Clock to

each slice

GND

LFEC10 Datasheet(PDF) 12 Page - Lattice Semiconductor