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LFEC10 Datasheet(PDF) 27 Page - Lattice Semiconductor |
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LFEC10 Datasheet(HTML) 27 Page - Lattice Semiconductor |
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27 / 163 page  2-24 Architecture Lattice Semiconductor LatticeECP/EC Family Data Sheet Figure 2-27. Input Register DDR Waveforms Figure 2-28. INDDRXB Primitive Output Register Block The output register block provides the ability to register signals from the core of the device before they are passed to the sysI/O buffers. The block contains a register for SDR operation that is combined with an additional latch for DDR operation. Figure 2-29 shows the diagram of the Output Register Block. In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D- type or latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0). Figure 2-30 shows the design tool DDR primitives. The SDR output register has reset and clock enable available. The additional register for DDR operation does not have reset or clock enable available. AB C D E F BD DI (In DDR Mode) D0 D2 DQS A C DQS Delayed IDDRXB LSR QA D ECLK QB DDRCLKPOL SCLK CE |
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