LFEC10 datasheet(31/163 Pages) LATTICE

31 / 163 page

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Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Polarity Control Logic

In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the

internal system Clock (during the READ cycle) is unknown.

The LatticeECP/EC family contains dedicated circuits to transfer data between these domains. To prevent setup

and hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is

used. This changes the edge on which the data is registered in the synchronizing registers in the input register

block. This requires evaluation at the start of each READ cycle for the correct clock polarity.

Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device

drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to

control the polarity of the clock to the synchronizing registers.

sysI/O Buffer

Each I/O is associated with a ﬂexible buffer referred to as a sysI/O buffer. These buffers are arranged around the

periphery of the device in eight groups referred to as Banks. The sysI/O buffers allow users to implement the wide

variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.

sysI/O Buffer Banks

LatticeECP/EC devices have eight sysI/O buffer banks; each is capable of supporting multiple I/O standards. Each

sysI/O bank has its own I/O supply voltage (VCCIO), and two voltage references VREF1 and VREF2 resources allow-

ing each bank to be completely independent from each other. Figure 2-34 shows the eight banks and their associ-

ated supplies.

In the LatticeECP/EC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCI-

X) are powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as ﬁxed threshold

input independent of VCCIO. In addition to the bank VCCIO supplies, the LatticeECP/EC devices have a VCC core logic

power supply, and a VCCAUX supply that power all differential and referenced buffers.

Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-

enced input buffers. In the LatticeECP/EC devices, some dedicated I/O pins in a bank can be conﬁgured to be a

reference voltage supply pin. Each I/O is individually conﬁgurable based on the bank’s supply and reference volt-

ages.

LFEC10 Datasheet(PDF) 31 Page - Lattice Semiconductor